The construction of minimal area power and ground nets for VLSI circuits

ABSTRACT

This paper deals with the problem of sizing power and ground nets in integrated circuits composed of modules, where the nets are routed in the channels between the modules. Constraints are assumed on allowable voltage drops between the chip's power and ground pads and the module's power and ground pins. Maximum current drain into each module is also assumed to be known. A procedure for determining the width of each branch in the power and ground trees is presented, where the objective is to minimize the area of the power and ground nets subject to several constraints, such as IR voltage drop and metal migration.

REFERENCES

• 1: D.P. Bertsekas, Constrained Optimization and Lagrange Multiplier Methods, Academic Press, 1982.
• 2: J. R. Black, "Electromigration failure modes in aluminium metalization for semiconductor devices", t'roeeedings IEEE, Vol. 5?, September 1969, pp. 1587-1594.
• 3: F.H,Branin, Jr., "The analysis and design of power distribution nets on LSI chips", IEEE Transaction8 on Circuit8 and Systernslg80, pp. 785-790.
• 4: Carver Mead , Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1979

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  J. Computer Applications

General Terms:
Algorithms, Design, Performance, Theory