Algorithms for automatic transistor sizing in CMOS digital circuits

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Algorithms for automatic transistor sizing in CMOS digital circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 781 - 784

Year of Publication: 1985

ISBN:0-8186-0635-5

Authors

William H. Kao	Xerox Corporation, Electronics Division, 701 S. Aviation Boulevard, MS Al-85, El Segundo, CA
Nader Fathi	Silicon General, Garden Grove, CA and Xerox Corporation, Electronics Division, 701 S. Aviation Boulevard, MS Al-85, El Segundo, CA
Chia-Hao Lee	Xerox Corporation, Electronics Division, 701 S. Aviation Boulevard, MS Al-85, El Segundo, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 27, Citation Count: 8

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper describes the algorithms for automatic transistor sizing (determination of device width and length) of CMOS digital circuits. In CMOS circuits, since power dissipation is small and not a limiting factor, the sizing algorithm is geared toward minimizing area. The program XTRAS (Xerox TRAnsistor Sizing Program) which determines transistor sizes as well as calculates path delays is described. Equations for the calculation of gate area, node capacitances, and rise and fall delays are given. Example circuits sized using XTRAS are compared and found to be within 10% of SPICE circuit simulations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L.W. Nagel, "SPICE2- A Compu~;er Program to Simulate Semiconductor Circuits", ERL-M520, University of California, Berkeley, May 1975.
	2	S. M. Kang," A Design of CMOS Polycells for LSI Circuits", IEEE Trans. on Circuits and Systems, Aug. 1981, pp. 838-843,
	3	M. I. Elmasry," Digital MOS Integrated Circuits", IEEE Press 1981, pp. 4-27.
	4	William H. Kao , Mohammad H. Movahed-Ezazi , Mark L. Sabiers, ARIES: A workstation based, schematic driven system for circuit design, Proceedings of the 21st conference on Design automation, p.301-307, June 25-27, 1984, Albuquerque, New Mexico, United States
	5	K. Hedlund, "Models and Algorithms for Transistor Sizing in NMOS Circuits", International Conference on CAD, Santa Clara, Nov. 1984.
	6	E. Lewis, "Optimization of Device Area and Overall Delay for CMOS VLSI Designs", Proceedings of the iEEE, June 1984, pp. 670-689.
	7	C. M. Lee and H. Soukup," An Algorithm for CMOS Timing and Area Optimization", IEEE J. of Solid State Circuits, Oct. 1984, pp. 781-787,
	8	R. E. Clark , R. N. Kubik , L. P. Phillips, Algorithm 164: orthogonal polynomial least squares surface fit, Communications of the ACM, v.6 n.4, p.162-163, April 1963 [doi>10.1145/366349.366440]

CITED BY 8

	Jonathan D. Pincus , Alvin M. Despain, Delay reduction using simulated annealing, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.690-695, July 1986, Las Vegas, Nevada, United States
	Shen Lin , M. Marek-Sadowska , Ernest S. Kuh, Delay and area optimization in standard-cell design, Proceedings of the 27th ACM/IEEE conference on Design automation, p.349-352, June 24-27, 1990, Orlando, Florida, United States
	Bradley S. Carlson , C. Y. Roger Chen, Performance enhancement of CMOS VLSI circuits by transistor reordering, Proceedings of the 30th international conference on Design automation, p.361-366, June 14-18, 1993, Dallas, Texas, United States
	Michel R. C. M. Berkelaar , Pim H. W. Buurman , Jochen A. G. Jess, Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.474-480, November 06-10, 1994, San Jose, California, United States
	Michel R. C. M. Berkelaar , Jochen A. G. Jess, Gate sizing in MOS digital circuits with linear programming, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	C. H. Allen Wu , Nels Vander Zanden , Daniel Gajski, A new algorithm for transistor sizing in CMOS circuits, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	Shen Lin , Malgorzata Marek-Sadowska, A fast and efficient algorithm for determining fanout trees in large networks, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	Fred W. Obermeier , Randy H. Katz, An electrical optimizer that considers physical layout, Proceedings of the 25th ACM/IEEE conference on Design automation, p.453-459, June 12-15, 1988, Atlantic City, New Jersey, United States