| Analysis of timing failures due to random AC defects in VLSI modules |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 22nd ACM/IEEE Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 709 - 714
Year of Publication: 1985
ISBN:0-8186-0635-5
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Downloads (6 Weeks): 7, Downloads (12 Months): 13, Citation Count: 9
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ABSTRACT
This paper presents an analytical model for projecting the yield loss due to random delay defects for modules or VLSI packages containing multiple semiconductor chips. A module to be analyzed is characterized by distribution of path delays. Statistical analysis is applied to obtain the distribution of delays caused by defects in logic circuits of LSI chips. The model uses these two distributions to calculate the probability that a module contains a path that does not meet the system timing requirements. All inputs to the model can be obtained much earlier than the availability of modules for actual testing. Therefore expected module yield loss due to delay defects can be projected before the modules are actually manufactured.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Robert Hitcho:k,Sz., Gozdon L. Smith, and David D. Cheng, "Timing Analysi= of Computer Hardware," IBM J. Res. Develop. 26,100-105, January 1982.
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Donald S. Cleveziey, "The Role of Testing In Achieving Zero Defects," Proceedings of the 1982 liCE International Test Conference, November 1982, pp. 248-253.
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C. C. Beh, K. H. Azya, C. E. Radke, and K. ~. Torku, "Do Stuck Fault Models Reflect Manufacturing Defects?," Pzoceeeding= of the 1982 IEEE International Test Conference, pp. $5--~2.
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D. B. Owen, "Handbook of Statistical Tables," Addison-Wesley, Reading,Mass., 1962, pp.,l-10.
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APL Statistical Libzazy, Fozm No. 5H20-184.1, IBM Corporation, Nhite Plains, N.Y., 1976, pp. 60-61.
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CITED BY 9
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Jing-Jia Liou , Li-C. Wang , Kwang-Ting Cheng , Jennifer Dworak , M. Ray Mercer , Rohit Kapur , Thomas W. Williams, Enhancing test efficiency for delay fault testing using multiple-clocked schemes, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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P. Girard , C. Landrault , S. Pravossoudovitch, A novel approach to delay-fault diagnosis, Proceedings of the 29th ACM/IEEE conference on Design automation, p.357-360, June 08-12, 1992, Anaheim, California, United States
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