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Integrated VLSI CAD systems at Digital Equipment Corporation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 543 - 548  
Year of Publication: 1985
ISBN:0-8186-0635-5
Authors
A. F. Hutchings  Digital Equipment Corporation, 77 Reed Rd., Hudson, MA
R. J. Bonneau  Digital Equipment Corporation, 77 Reed Rd., Hudson, MA
W. M. Fisher  Digital Equipment Corporation, 77 Reed Rd., Hudson, MA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 10,   Citation Count: 2
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ABSTRACT

This paper presents an overview of the experience at Digital Equipment Corporation's LSI plant with VLSI IC CAD systems. Digital's VLSI CAD group has been involved in the development and use of two generations of VLSI CAD systems, and the paper will discuss these experiences, emphasizing some of the trade-offs in the selection of the individual tools as well as the design of the kernel and data manager parts of the systems. The development of the first generation system and tools occurred in parallel with a major multi-chip IC design project 13 and in conjunction with the evolution of a major silicon (NMOS) process for Digital. While a great deal was salvaged from this severe learning experience (and note that all the IC's were nevertheless successfully completed), many aspects of the tools and system needed a complete overhaul for our next generation of IC's. We are now entering the phase of utilizing the results of this second generation custom MOS CAD system development. In parallel, we embarked on a separate and yet ultimately complementary development - that of a set of semi-custom CAD systems and associated tools. These too are now just being exploited to the full by Digital's VLSI IC design community. Our first generation (N)MOS custom system, based around the CHAS kernel, was used to design over 12 large IC's (including 32-bit microprocessors). We are now developing a second generation kernel data manager to replace CHAS, as well as semi-custom systems supporting gate array, standard cell and polycell (macrocell) capabilities.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J.C.Mudge. C.Peters, G.M.Tarolli, "A VLSI Chip Assembler", pp329-356. Design Methodologies for VLSI Circuits (Sijthoff and Noordhoff 1982), (Ed. P.G. Jespers et al.)
 
2
M.A.Kearney. "DECSIM: A Multi-level Simulation System For Digital Design". pp206-209, Proceedings of the 1984 ICCD Conference on Computer Design.
 
3
Roy R. Rezac, Leslie Turner Smith, "Methodology For And Results From The Use Of A Hardware Logic Simulation Engine", pp457-461 Proceedings of the 1984 ICCD Conference on Computer Design.
 
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Katz. R. H. "Managing the Chip Design Database" IEEE Computer, December. 1983.
 
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Lampson, Butler W., "Hints for Computer System Design". IEEE Software. January. 1984.
 
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Newton. A. Richard, Notes from CAD Course. Digital Equipment Corporation, 1984.
 
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"CHAS Documentation Set", Internal Documentation, Digital Equipment Corporation. 1984.
 
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EDIF, Electronic Design Interchange Format. Version 0.8. Henry Alward, Technical Coordinator. Tektronix, Beaverton, OR., 1984.
 
13
Johnson. William N.. "A VLSI Superminicomputer CPU" Digital Equipment Corporation. 1984 IEEE International Solid-State Circuits Conference.
 
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Collaborative Colleagues:
A. F. Hutchings: colleagues
R. J. Bonneau: colleagues
W. M. Fisher: colleagues