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Synthesis of optimal clocking schemes
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 489 - 495  
Year of Publication: 1985
ISBN:0-8186-0635-5
Authors
Nohbyung Park  Department of Electrical Engneering-Systems, University of Southern California, Los Angeles, California
Alice Parker  Department of Electrical Engneering-Systems, University of Southern California, Los Angeles, California
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Citation Count: 8
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ABSTRACT

Clocking scheme synthesis includes the partitioning of functions into time steps, the number of clock phases, the length of each phase, (i.e. how to pipeline) and the assignment of functions to clock phases; each of these choices affects performance. Some important problems of clocking scheme synthesis are examined. Two efficient and powerful algorithms which synthesize near optimal clocking schemes have been programmed. These algorithms are applied to synthesis and/or performance evaluation of a design in progress. Optimizing the speed of a previously designed system is also considered.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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L. W. Cotton, Circuit Implementation of High- Speed Pipeline Systems, In Proceedings of F JCC, pages 480-504. AFIPS, 1065.
 
3
E. Davidson, et. al., Effective Control for Pipelined Computers, In COMPCON Digest, pages 181-184. 1975.
 
4
L. Hafer and A. Parker, A Formal Method for the Specification Analysis, and Design of Register- Transfer Level Digital Logic, IEEE Trans. on Computer-Aided Design CAD-2(1), Jan. 1983.
 
5
Hewlett-Packard, HP 1000 E-Series and F-Series Computer Microprogramming Reference Manual Hewlett-Packard, 1978.
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P. M. Kog~e, The Architecture of th'pelined Computers, McGraw-Hill, New York, N.Y., 1981.
 
8
A. Nagle, Automatic Design of Sequencers ?or The Control of Digital Hardware, PhD thesis, Carnegie-Mellon University, October, 1980.
 
9
N. Park and A. Parker, Synthesis of Optimal Clocking Schemes for Digital Systems, Technical Report DISC/84-1, Dept. of EE-Systems, University of Southern California, May, 1984.
 
10
N. Park and A. Parker, Synthesis of Optimal Pipeline Clocking Schemes, Technical Report DISC/85-1, Dept. of EE-Systems, University of Southern California, January, 1985.

CITED BY  8

Collaborative Colleagues:
Nohbyung Park: colleagues
Alice Parker: colleagues