PLINT layout system for VLSI chips

ABSTRACT

PLINT is a comprehensive VAX based VLSI chip layout software system. Important features include (1) standard cell row structure layout (POLYPLINT) or randomly placed and sized rectangular macro cells (MACPLINT), (2) unlimited hierarchy, (3) automatic macrocell generation for next hierarchy level, (4) 100% routing, (5) very large chip size and/or complexity capability, (6) power and ground bus routing for both POLYPLINT and MACPLINT, (7) parameterization for generic use and (8) ability to intermix standard cell and macrocell layout when the macrocells are restricted to left or right chip edges. The software is being used at several General Electric sites for VLSI chip development. Numbers of matching categories: (1), (2), (5) keywords: IC layout, computer-aided design, VLSI, IC placement, IC routing, standard cell layout, macrocell layout.

REFERENCES

• 1: "Global Channel Routing by Pairing," Charles M. Fiduccia, General Electric R&D Center, Schenectady, NY, June 1983.
• 2: "Placement and Routing Algorithms for Hierarchical Integrated Circuit Layout," Bryan Preas, PhD dissertation, Stanford University, August 1979.
• 3: "A Bu~ Router for IC Layout," H. Lie, C. Horng, Igth Design Auto(nation-Conference, IEEE, 1982
• 4: "A 'Greedy Router' Channel Router," Ronald L. Rivest, Charles M. Feduccia MIT Laboratory for Computer Science, Cambridge, HA, and General Electric R&O Center, Schenectady, NY, March 1981,

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Placement and routing

  J. Computer Applications

General Terms:
Design, Performance, Theory

Keywords:
IC layout, IC placement, IC routing, VLSI, computer-aided design, macrocell layout, standard cell layout