ACM Home Page
Please provide us with feedback. Feedback
Synthesis by delayed binding of decisions
Full text PdfPdf (850 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 367 - 373  
Year of Publication: 1985
ISBN:0-8186-0635-5
Authors
Jayanth V. Rajan  Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
Donald E. Thomas  Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 8,   Citation Count: 7
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/317825.317914
What is a DOI?

ABSTRACT

This paper presents a method for the automatic synthesis of digital systems from behavioral descriptions. Subtasks in complex problem solving activities like synthesis often interact. As a result, premature binding of decisions can lead to poor designs. Better design choices can be made if decisions are postponed until adequate information is available to make them. The paper details how delayed binding of decisions is implemented in a program called SUGAR and how subtasks are organized so that they cooperate with one another in designing a system.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S.W. Director, A.C. Parker, D.P. Siewiorek, and D.E. Thomas, '~ Design Methodology and Computer Aids for Digital VLSI Systems," IEEE Trans. Circuit8 Systems CAS-28(7) pp. 634-645 (July 1981).
 
2
M.R. Barb~cci, 'Instruction Set Specifications (ISPS): The Notation and its Applications," IEEE Trans. Computers C,-30(1)(Jan. 1981).
 
3
D.E. Thomas, C.Y. Hitchcock III, T.J. Kowalski, J.V. Rajan, and R.A. Walker, 'IA.utomatic Data Path Synthesis," Computar 16(12)pp. 59-70 (Dec. 1983).
 
4
 
5
B.W. Leverett, R.G.G. Cartel, S.O. Hobbs, J.M. Newcomer, A.H. Reiner, B.R. Schatz, and W.A. Wuli', '~An Overview of the Production Quality Compiler-Compiler Project," Computer la(S)(hug., 1980).
 
6
L.J. Hafer and A.C. Parker, '~ Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic," IEEE Trans. Computer-Aided De.sign CA.D-2(1)pp. 4-18 (Jan. 1983).
 
7
 
8
S.C. Johnson, 'Hierarchical Clustering Schemes," PsychometTika 32 pp. 241-254 (1967).
 
9
MOS Technology, Inc., MCS6500 Microcomputer Family Hardware Manual. ff~n. 1976.
 
10
J.A. Fisher, 'Trace Scheduling: A Technique for Global Microcode Compaction," 1EEE Trans. Computer8 0-30(7) pp. 478-490 (July 1981).

CITED BY  7

Collaborative Colleagues:
Jayanth V. Rajan: colleagues
Donald E. Thomas: colleagues