| Synthesis by delayed binding of decisions |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 367 - 373
Year of Publication: 1985
ISBN:0-8186-0635-5
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Authors
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Jayanth V. Rajan
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Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
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Donald E. Thomas
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Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 7
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ABSTRACT
This paper presents a method for the automatic synthesis of digital systems from behavioral descriptions. Subtasks in complex problem solving activities like synthesis often interact. As a result, premature binding of decisions can lead to poor designs. Better design choices can be made if decisions are postponed until adequate information is available to make them. The paper details how delayed binding of decisions is implemented in a program called SUGAR and how subtasks are organized so that they cooperate with one another in designing a system.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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S.W. Director, A.C. Parker, D.P. Siewiorek, and D.E. Thomas, '~ Design Methodology and Computer Aids for Digital VLSI Systems," IEEE Trans. Circuit8 Systems CAS-28(7) pp. 634-645 (July 1981).
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M.R. Barb~cci, 'Instruction Set Specifications (ISPS): The Notation and its Applications," IEEE Trans. Computers C,-30(1)(Jan. 1981).
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D.E. Thomas, C.Y. Hitchcock III, T.J. Kowalski, J.V. Rajan, and R.A. Walker, 'IA.utomatic Data Path Synthesis," Computar 16(12)pp. 59-70 (Dec. 1983).
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B.W. Leverett, R.G.G. Cartel, S.O. Hobbs, J.M. Newcomer, A.H. Reiner, B.R. Schatz, and W.A. Wuli', '~An Overview of the Production Quality Compiler-Compiler Project," Computer la(S)(hug., 1980).
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L.J. Hafer and A.C. Parker, '~ Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic," IEEE Trans. Computer-Aided De.sign CA.D-2(1)pp. 4-18 (Jan. 1983).
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S.C. Johnson, 'Hierarchical Clustering Schemes," PsychometTika 32 pp. 241-254 (1967).
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MOS Technology, Inc., MCS6500 Microcomputer Family Hardware Manual. ff~n. 1976.
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J.A. Fisher, 'Trace Scheduling: A Technique for Global Microcode Compaction," 1EEE Trans. Computer8 0-30(7) pp. 478-490 (July 1981).
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CITED BY 7
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D. E. Thomas , E. M. Dirkes , R. A. Walker , J. V. Rajan , J. A. Nestor , R. L. Blackburn, The system architect's workbench, Proceedings of the 25th ACM/IEEE conference on Design automation, p.337-343, June 12-15, 1988, Atlantic City, New Jersey, United States
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Michael C. McFarland , Alice C. Parker , Raul Camposano, Tutorial on high-level synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.330-336, June 12-15, 1988, Atlantic City, New Jersey, United States
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T. Shinsha , T. Kubo , Y. Sakataya , J. Koshishita , K. Ishihara, Incremental logic synthesis through gate logic structure identification, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.391-397, July 1986, Las Vegas, Nevada, United States
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