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A knowledge based system for selecting a test methodology for a PLA
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 259 - 265  
Year of Publication: 1985
ISBN:0-8186-0635-5
Authors
M. A. Breuer  Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
Xi-an Zhu  Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 6,   Citation Count: 7
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ABSTRACT

Testability is a very important aspect of VLSI circuits. Numerous design for testability (DFT) methods exist. Often designers face the complex problem of selecting the best DFT techniques for a particular chip under a set of design constraints and goals. In order to aid in designing testable circuits, a prototype knowledge based system has been developed which simulates a human expert on design of testable PLAs. The system, described in this paper, has knowledge about testable PLA design methodologies and is able to negotiate with the user so as to lead the user through the design space to find a satisfactory solution. A new search strategy, called reason analysis, is introduced.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Breuer, M.A. and A.D. Friedman, Diagno~i~ and Reliable DeMgn of Digital Systems, Computer Science Press, Rochville, MD, 1976.
 
2
Hong, S. J. and D. L. Ostapko, "FITPLA: A programmable logic array for functional independent testing", Digest of Paper8 l Oth International Symposium F~utt-Tolerant Computing, October lg80, pp. 131-136.
 
3
Daehn, W. and J. Mucha, "A hardware approach to selftesting of large programmable logic arrays", IEEE Trans. on Computers, Vol. C-30, November 1981, pp. 829-833.
 
4
Saluja, K.K., K. Kinoshita and H. Fujiwara, "An easily testable design of programmable logic arrays for multiple faults", {EEE Trarts. on Computers, Vol. C-32, November 1983, pp. 1038-1046.
 
5
Fujiwara, H. and K. Kinoshita, "A design of programmable logic arrays with universal tests", IEEE Trans. on Computers, Vol. C-30, November 1981, pp. 823-828.
 
6
Hassan, S. Z., "Testing PLAs using multiple parallel signature analyzers", CRC Technical Report 82-9, Stanford University, June 1982.
 
7
Khakbaz, J. and E. j. McCluskey, "Concurrent error detection and testing for large PLAs", CRC Technical Report 81-14, Stanford University, September i981.
 
8
Yajima, S. and T. Aramaki, "Autonomously testable programmable logic arrays", Digest of Paper~ llth International Symposium Fault-Tolerant Computing, June 1981, pp. 41-43.
 
9
 
10
Stallman, R.M. and G.J. Sussman, "Forward reasoning and dependency-directed backtracking in a system for computeraided circuit analysis", Artificial Intelligence, Vol. 9, February 1977, pp. 135-196.
 
11
Shortliffe, E.H., Computer-based medical consultatiort: MYCIN, American Elsevier, New York, 1976.
 
12
Chu Y-Y. and W. H. Crooks, "Man-machine communication in computer-aided remote manipulation", Technical report PATR-1034-80-3, Perceptronics, Woodland Hills, CA., 1980.
 
13
Breuer, M. A., "A methodology for the design of testable VLSI chips", submitted to IEEE Design & Test of Computers.

CITED BY  7