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ABSTRACT
The Design Automation Assistant is a knowledge-based expert-system, KBES, that generates a technology-independent list of operators, registers, data paths and control signals from an algorithmic description of a VLSI system. One merit of codifying knowledge in a KBES is that it can be easily quantified and qualified. This paper takes a retrospective on that codified knowledge base, examining what has been learned about VLSI design. It discusses both the major steps in the implementation design process and the extent to which each rule embodies domain knowledge. Finally, the paper provides an example design with typical rules from each of the major steps in the implementation design process.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Director, S. W., Parker, A. C., Siewiorek, D. P., and Thomas, D. E., "A design methodology and computer aids for digital VLSI systems," IEEE Transactions on
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Thomas, D. E., Hitchock, C. Y. iii, Kowalski, T. J., Rajah, J. V., anti Walker, R., "'Automatic Data Path Synthesis," Computer 16(12) pp. 59-70 (December, 1983).
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4
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Kowalski, T. J. and Thomas, D. E., "The VLSI Design Automation Assistant" First Steps," TwemT-sixth IEEE Computer Society International Conference, pp. 126 - 130 (February 28, 1983).
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Kowalski, T. J. and Thomas, D. E., "The VLSI Design Automation Assistant: An IBM System/370 Design," Design and Test cf Computers 1 (1) pp. 60-69 (February, 1984).
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Kowalski, T. J., Geiger, D. J., Wolf, W. H., and Fichtner, W., "The VLSI Design Automation Assistant: A Birth In Industry," IEEE lnternation Symposium on Circuits and Systems, (June 5, 1985).
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Forgy, C. L., OPS5 User's Manual, Department of Computer Science, Carnegie-Mellon University (July, 1981).
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Rose, M, A., Structured Control Flow: An Architectural Technique figr improving Control Flow Performance, Masters thesis, Department of Electrical Engineering, Carnegie-Mellon University (November, 1983).
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Kernighan, B. W. and Lin, S., "An Efficient Heuristic Procedure for Partitioning Graphs," Bell Sys. Tech. J. 49(2) pp. 291-308 (I 970).
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12
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Barbacci, M. R., Barnes, G. E., Cattell, R. G., and Siewiorek, D. P., The ISPS Computer Description Language, Department of Computer Science,
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15
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Kowalski, T. J., Computer-Aided Cost Estimation from Implementation Specifications, (unpublished).
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CITED BY 11
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t. Cesear , E. Iodice , C. Tsareff, PAMS: an expert system for parameterized module synthesis, Proceedings of the 24th ACM/IEEE conference on Design automation, p.666-671, June 28-July 01, 1987, Miami Beach, Florida, United States
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Takao Saito , Hiroyuki Sugimoto , Masami Yamazaki , Nobuaki Kawato, A rule-based logic circuit synthesis system for CMOS gate arrays, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.594-600, July 1986, Las Vegas, Nevada, United States
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R. Harjani , R. A. Rutenbar , L. R. Carley, A prototype framework for knowledge-based analog circuit synthesis, Proceedings of the 24th ACM/IEEE conference on Design automation, p.42-49, June 28-July 01, 1987, Miami Beach, Florida, United States
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