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PATEGE: an automatic DC parametric test generation system for series gated ECL circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 212 - 218  
Year of Publication: 1985
ISBN:0-8186-0635-5
Authors
Takuji Ogihara  Mitsubishi Electric Corporation, 325 Kamimachiya, Kamakura 247, Japan
Shuichi Saruyama  Mitsubishi Electric Corporation, 325 Kamimachiya, Kamakura 247, Japan
Shinichi Murai  Mitsubishi Electric Corporation, 325 Kamimachiya, Kamakura 247, Japan
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

For ECL circuits. DC parametric tests such as input current (IIL IIH), reference voltage (VBB), and power supply current (ICC) tests are executed as well as functional tests. This paper describes: an automatic DC parametric test generation system PATEGE for the series gated ECL circuits. PATEGE can automatically generate the test patterns and calculate the expected values for IIL, IIH, VBB and ICC tests.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T.W. Wi I Jams and l~ P. Parker. ~ Dee~ign for Testzb i I ity - A Servey " IEEK Trans. Comput.. C-31. pp. 2-15, JanL 198Z
 
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P. Goel. " An Implicit Enuneratio. Algorithm to Generate Test for Combinational t~)gic Circuits ". FTCS 1(~ pp. 145-151, Oct. 1980.
 
4
K FujimLra and T. Shimonc~ " On the Acceleration of Test Generation Algorithms " FI~',S 13, pp. 98-105, Jun. 198~
 
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Collaborative Colleagues:
Takuji Ogihara: colleagues
Shuichi Saruyama: colleagues
Shinichi Murai: colleagues