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ABSTRACT
The CAD-tool PROTEST (Probabilistic Testability Analysis) is presented. PROTEST estimates for each fault of a combinational circuit its detection probability which can be used as a testability measure. Moreover it calculates the number of random test patterns which must be generated in order to achieve the required fault coverage.
It is also demonstrated that the fault coverage will increase and the necessary number of random patterns will drastically decrease, if each primary input is stimulated by test patterns having specific probabilities of being logical “1”. PROTEST uses this fact and determines for each input the optimal signal probability for a randomly generated pattern.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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AgAg75
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P. Agrawal, V.D. Agrawal ; Probabllistic Analysis of Random Test Generat ion Method for Irredundant Combinational Logic Networks; IEEE Trans. on Comput. , Vol. C-24, No. 7, July 1975
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AgJa84
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AgMe82
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Agrawal, V. D., Mercer, M. R. ; Testability Measures -What Do They Tell Us; International Test Conference, 1982, pp. 391 - 396
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BDS84
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J. Savir, G.S. Ditlow, P.H. Bardell ; Random Pattern Testability ; IEEE, Trans. Comp., Vol. C-33, No. I, Jan. 1984
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CKR84a
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R. Camposano, A. Kunzmann, W. Rosenstiel; Automatic Data Path Synthesis from DSL Spezlfications; IEEE, Proc. of Int. Conf. on Computer Design, ICCD, 1984
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EiWi77
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Goel81
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P. Goel; An implicit enumeration algorithm to generate tests for combinational logic circuits ; IEEE Trans. on Comp. , Vol. C-30, no. 3, March 1981
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Hart80
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R.W. Hartens te in ; VLSI-Baustelne in geringen Stueckzahlen fuer Spezia lanwendungen ; Elektronlsche Rechenanlagen, Heft 4, 1980
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HeLe83
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J.H. Heckmaier, D. Lelsengang; Fehlererkennung mit Signaturanalyse ; Elektron. Rechenanl. 25, 1983, H. 3, 109 - 116
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KuWu84
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A. Kunzmann, H.-J. Wunderlich; Stelgerung der Efflzlenz beim Test mlt Zufallsmustern Report 19/84 at the Faculty for Informatlcs, University of Karlsruhe, October 1984
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Much81
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J. Mucha; Hardware Techniques for Testing VLSI Circuits Based on Built-In Test ; Proc. COMPCON 81 , Feb. 1981
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MuSa81
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E.I. Muehldorf, A.D. Savkar; LSI Logic Testing - An Overview; IEEE Trans. on Computers, Vol. C-30, No. i, January 1981
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Nils80
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SCHD84
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CITED BY 19
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M. B. Santos , I. C. Teixeira , J. P. Teixeira , S. Manich , L. Balado , J. Figueras, On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level, Journal of Electronic Testing: Theory and Applications, v.20 n.4, p.345-355, August 2004
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