Yet another silicon compiler

ABSTRACT

In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface logic. A novel technique for layout generation yields cells whose densities approach hand-crafted designs. Two-layer metal NMOS and CMOS technologies are supported, with flexible design rules. In addition to layout synthesis, logic, schematic and graph diagrams are generated directly from a powerful internal data base. The compiler, which runs under the UNIX^^ operating system, includes a menu-driven multi-windowing user environment.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.4 Microprogram Design Aids
          Subjects: Languages and compilers

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies
      B.7.2 Design Aids
          Subjects: Layout; Simulation

  J. Computer Applications

General Terms:
Design, Languages, Performance, Theory