| A fully automatic hierarchical compactor |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 69 - 75
Year of Publication: 1985
ISBN:0-8186-0635-5
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Authors
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George Entenman
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Microelectronics Center of North Carolina, Research Triangle Park, North Carolina
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Stephen W. Daniel
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Microelectronics Center of North Carolina, Research Triangle Park, North Carolina
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| Bibliometrics |
Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 9
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ABSTRACT
A fully automatic hierarchical compactor has been developed to translate hierarchical, symbolic cell designs into artwork. The hierarchical compactor takes advantage of the fact that a typical hierarchical design uses the same cell in several different places. Each cell is first examined in all of its contexts. The leaf-cell compactor next compacts each leaf-cell to its minimum possible size in its worst-case environment. The last step is to abut instances of the cells according to the original symbolic layout; some grid line spacings may be increased to avoid breaking wires. The compactor is implemented as a set of rule-driven procedures that find all technology dependent information in technology description files. The result of this strategy is a technology-independent compactor that produces compact, error-free artwork.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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ACKL83
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ACKLAND, BRYAN AND NElL WESTE, "An Automatic Assembly Tool for Virtual Grid Symbolic Layout," Proc. VLSI '83 Norway, (Aug. 1983).
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BOYE83
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BOYER, DAVID G. AND NElL H. E WEST~ "Virtual Grid Compaction Using the Most Recent Layers Algo~ rithm,' Proc. ICCAD-8$, (Sept. 1983).
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DANI85a
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DANmL, STEPHEN, "Technology Independent Compaction for Symbolic Virtual-Grid Layouts," MCNC Technical Report {forthcoming} (Jan. ~985).
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DANI85b
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DANn~ STEPHEN, "Rectilinear Anti- Feature Elimination by Polygon Algebra," MCNC Technical Report
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(Jan. 1985).
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ROSE83b
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ROSENBERG, JONATHAN B. AND NElL H. E. WESTE, "ABCD - A Better Circuit Description," MCNC Tech. Rep. No. 4983-01, Microelectronics Center of NC, RTP, NC 27709 (Feb. 1983).
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SMIT85
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SMITH, PHILIP O. AND STEPHEN W. DANIEL, 'l'he Master Technology Files System for Technology Independence," Proc. 22rid Design Automation Conf. {forthcoming}, (June 1985).
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WATA84
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WATANABE, HtROYUK~, IC Layout Generation and Compaction Using Mathematical Optimization, Semiconductor Research Corporation, Research Triangle Park NC (February 1984).
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CITED BY 9
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W. Kim , J. Lee , H. Shin, A new hierarchical layout compactor using simplified graph models, Proceedings of the 29th ACM/IEEE conference on Design automation, p.323-326, June 08-12, 1992, Anaheim, California, United States
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L. S. Nyland , S. W. Daniel , D. Rogers, Improving virtual-grid compaction through grouping, Proceedings of the 24th ACM/IEEE conference on Design automation, p.305-310, June 28-July 01, 1987, Miami Beach, Florida, United States
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