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A fully automatic hierarchical compactor
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 22nd ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 69 - 75  
Year of Publication: 1985
ISBN:0-8186-0635-5
Authors
George Entenman  Microelectronics Center of North Carolina, Research Triangle Park, North Carolina
Stephen W. Daniel  Microelectronics Center of North Carolina, Research Triangle Park, North Carolina
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Citation Count: 9
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ABSTRACT

A fully automatic hierarchical compactor has been developed to translate hierarchical, symbolic cell designs into artwork. The hierarchical compactor takes advantage of the fact that a typical hierarchical design uses the same cell in several different places. Each cell is first examined in all of its contexts. The leaf-cell compactor next compacts each leaf-cell to its minimum possible size in its worst-case environment. The last step is to abut instances of the cells according to the original symbolic layout; some grid line spacings may be increased to avoid breaking wires. The compactor is implemented as a set of rule-driven procedures that find all technology dependent information in technology description files. The result of this strategy is a technology-independent compactor that produces compact, error-free artwork.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
ACKL83
ACKLAND, BRYAN AND NElL WESTE, "An Automatic Assembly Tool for Virtual Grid Symbolic Layout," Proc. VLSI '83 Norway, (Aug. 1983).
 
BOYE83
BOYER, DAVID G. AND NElL H. E WEST~ "Virtual Grid Compaction Using the Most Recent Layers Algo~ rithm,' Proc. ICCAD-8$, (Sept. 1983).
 
DANI85a
DANmL, STEPHEN, "Technology Independent Compaction for Symbolic Virtual-Grid Layouts," MCNC Technical Report {forthcoming} (Jan. ~985).
 
DANI85b
DANn~ STEPHEN, "Rectilinear Anti- Feature Elimination by Polygon Algebra," MCNC Technical Report
 
forthcoming
(Jan. 1985).
 
OUST84
OUSTERHOUT, JOHN K~ "Comer Stitching: A Dam-Structuring Technique for VLSI Layout Tools," IEEE Trans. on CAD CAD-3(1) pp. 87-100 (Jan. 1984).
 
ROSE83b
ROSENBERG, JONATHAN B. AND NElL H. E. WESTE, "ABCD - A Better Circuit Description," MCNC Tech. Rep. No. 4983-01, Microelectronics Center of NC, RTP, NC 27709 (Feb. 1983).
 
SMIT85
SMITH, PHILIP O. AND STEPHEN W. DANIEL, 'l'he Master Technology Files System for Technology Independence," Proc. 22rid Design Automation Conf. {forthcoming}, (June 1985).
 
WATA84
WATANABE, HtROYUK~, IC Layout Generation and Compaction Using Mathematical Optimization, Semiconductor Research Corporation, Research Triangle Park NC (February 1984).

CITED BY  9

Collaborative Colleagues:
George Entenman: colleagues
Stephen W. Daniel: colleagues