| ACORN: a local customization approach to DCVS physical design |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 22nd ACM/IEEE Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 32 - 38
Year of Publication: 1985
ISBN:0-8186-0635-5
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Authors
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Ellen J. Yoffa
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IBM Thomas J. Watson Research Center, Yorktown Heights, New York
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Peter S. Hauge
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IBM Thomas J. Watson Research Center, Yorktown Heights, New York
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| Bibliometrics |
Downloads (6 Weeks): 6, Downloads (12 Months): 12, Citation Count: 6
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ABSTRACT
Differential cascode voltage switch (DCVS) trees are high performance, high functionality CMOS circuits, which, because they have a large number of inputs and internal connections, are difficult to wire on a large scale. Wirability is substantially improved by local customization at the tree level. This paper describes a DCVS customization procedure that exploits the fact that a Boolean function has more than one physical realization. Using ACORN, an automated physical design system based on this concept, we have placed and wired several designs, the largest of which is a group of three interconnected macros comprising approximately 800 DCVS trees.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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L. G. Heller, W. R. Griffin, J. W. Davis and N. G. Thoma, "Cascode 'Voltage Switch Logic: A Differential CMOS Logic Family," 31st IEEE International Solid- State Circuits Conference, Digest of Technical Papers, 1984, pp. 16-17.
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C. K. Erdelyi, W. P. Griffin and R. D. Kilmoyer, "Cascode Voltage Switch Logic Design," VLSI Design, vol. V, 1984, pp. 78-86.
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R. K. Brayton, C. L. Chen, C. T. McMullen, R. H. J. M. Otten and Y. J. Yamour, "Automated implementation of Switching Functions as Dynamic CMOS Circuits," Proceedings of the IEEE Custom Integrated Circuits Conference, 1984.
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R. K. Brayton and C. T. McMullen, "The Decomposition and Factorization of Boolean Expressions," Proceedings of the International Symposium on Circuits and Systems, Rome, 1982, pp. 49-54.
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T. Uehara and W. M. vanCleemput, "Optimal Layout of CMOS Functional Arrays," I}EEE Transactions on Computers, vol. C-30, 1981, pp. 2,05-312.
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M. D. F. Schlag, E. J. Yoffa, P. S. Hauge, and C. K. Wong, "A Method for Improving Cascode-Switch Macro Wirability," IEEE Trans. CAD-IC, vol. 4, 1985, pp. 150-155.
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CITED BY 6
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B. P. Serlet, Fast, small, and static combinatorial CMOS circuits, Proceedings of the 24th ACM/IEEE conference on Design automation, p.451-458, June 28-July 01, 1987, Miami Beach, Florida, United States
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Knut M. Just , Edgar Auer , Werner L. Schiele , Alexander Schwaferts, PALACE: a layout generator for SCVS logic blocks, Proceedings of the 27th ACM/IEEE conference on Design automation, p.468-473, June 24-27, 1990, Orlando, Florida, United States
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