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Way-predicting set-associative cache for high performance and low energy consumption
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents
San Diego, California, United States
Pages: 273 - 275  
Year of Publication: 1999
ISBN:1-58113-133-X
Authors
Koji Inoue  Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN
Tohru Ishihara  Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN
Kazuaki Murakami  Department of Computer Science and Communication Engineering Kyushu University, 6-1 Kasuga-Koen, Kasuga, Fukuoka 816-8580 JAPAN
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 20,   Downloads (12 Months): 67,   Citation Count: 57
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Ghose, K., and Kemble, M. B, "Energy Efficient Cache Organizations for Superscalar Processors," Power-Driven Microarchitecture Workshop In Conjunction With ISCA98 in Barcelona, http://www.cs.colorado.ed u/ grunwald/LowPowerWorkshop/, June 1998.
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CITED BY  57

Collaborative Colleagues:
Koji Inoue: colleagues
Tohru Ishihara: colleagues
Kazuaki Murakami: colleagues