Instruction fetch energy reduction using loop caches for embedded applications with small tight loops

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Instruction fetch energy reduction using loop caches for embedded applications with small tight loops

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 267 - 269

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Lea Hwang Lee	M-CORE Technology Center, Motorola, Inc., P.O. Box 6000, MD TX77/F51, Austin, TX
Bill Moyer	M-CORE Technology Center, Motorola, Inc., P.O. Box 6000, MD TX77/F51, Austin, TX
John Arends	M-CORE Technology Center, Motorola, Inc., P.O. Box 6000, MD TX77/F51, Austin, TX

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 18, Citation Count: 34

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	N. Bellas, I. Hajj and C. Polychronopoulos, "A New Scheme for I-Cache energy reduction in High-Performance Processors," Power Driven Microarchitecture Workshop, held in conjunction with ISCA 98, Barcelona, Spain, June 28th 1998.
	2	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	3	L.H. Lee, J. Scott, B. Moyer and J. Arends, "Low-Cost Branch Folding for Embedded Applications with Small Tight Loops," Int'l Workshop on Compiler and Architecture Support for Embedded Computing Systems, Washington D.C., December 1998.
	4	M.CORE Reference Manual, Motorola Inc., 1997.
	5	B. Moyer, L. H. Lee and J. Arends, "Data Processing System Having a Cache and Method Therefor" US Patent, no. 5,893,142, 6th April, 1999.
	6	Ching-Long Su , Alvin M. Despain, Cache design trade-offs for power and performance optimization: a case study, Proceedings of the 1995 international symposium on Low power design, p.63-68, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224093]

CITED BY 34

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	Frank Vahid , Ann Gordon-Ross, A self-optimizing embedded microprocessor using a loop table for low power, Proceedings of the 2001 international symposium on Low power electronics and design, p.219-224, August 2001, Huntington Beach, California, United States
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	Jude A. Rivers , Sameh Asaad , John-David Wellman , Jaime H. Moreno, Reducing instruction fetch energy with backwards branch control information and buffering, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Stephen Hines , David Whalley , Gary Tyson, Adapting compilation techniques to enhance the packing of instructions into registers, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
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	Ahmad Zmily , Christos Kozyrakis, A low power front-end for embedded processors using a block-aware instruction set, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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	Yuki Kobayashi , Murali Jayapala , Praveen Raghavan , Francky Catthoor , Masaharu Imai, Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.2, p.604-612, February 2008
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