Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

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Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 252 - 254

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Ali Keshavarzi	MicroComputer Research Labs, Intel Corporation, Hillsboro, OR
Siva Narendra	MicroComputer Research Labs, Intel Corporation, Hillsboro, OR
Shekhar Borkar	MicroComputer Research Labs, Intel Corporation, Hillsboro, OR
Charles Hawkins	The University of New Mexico, Intel Corporation, Hillsboro, OR
Kaushik Roy	Purdue University, Intel Corporation, Hillsboro, OR
Vivek De	MicroComputer Research Labs, Intel Corporation, Hillsboro, OR

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 73, Citation Count: 12

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. Kuroda et. al., IEEE JSSC, Nov. 1996, pp. 1770-1779
	2	T. Kobayashi et. al., 1994 Proc. of CICC, pp. 271-274
	3	K. Seta et. al., 1995 ISSCC Tech. Dig., pp. 318-319
	4	S. Thompson et. al., 1997 Symp. VLSI Tech., pp. 69-70
	5	Ali Keshavarzi , Kaushik Roy , Charles F. Hawkins, Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs, Proceedings of the IEEE International Test Conference, p.146-155, November 03-05, 1997
	6	J.R. Brews, Chp. 3, High Speed Semiconductor Devices, ed. S.M. Sze, John Wiley & Sons, 1990
	7	M. Chen et. al., IEEE EDL, April 1998, pp. 134--136

CITED BY 12

	A. Keshavarzi , S. Ma , S. Narendra , B. Bloechel , K. Mistry , T. Ghani , S. Borkar , V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design, p.207-212, August 2001, Huntington Beach, California, United States
	Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Katsuhiro Seta , Toshiyuki Furusawa, Automated selective multi-threshold design for ultra-low standby applications, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Hyo-Sig Won , Kyo-Sun Kim , Kwang-Ok Jeong , Ki-Tae Park , Kyu-Myung Choi , Jeong-Taek Kong, An MTCMOS design methodology and its application to mobile computing, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Davood Shahrjerdi , Bahman Hekmatshoar , Ali Khakifirooz , Ali Afzali-Kusha, Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits, Integration, the VLSI Journal, v.38 n.3, p.505-513, January 2005
	Ali Keshavarzi , Kaushik Roy , Charles F. Hawkins , Vivek De, Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.863-870, October 2003
	Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Yuh-Fang Tsai , David E. Duarte , N. Vijaykrishnan , Mary Jane Irwin, Characterization and modeling of run-time techniques for leakage power reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.11, p.1221-1232, November 2004
	Nikhil Jayakumar , Sandeep Dhar , Sunil P. Khatri, A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Steven M. Martin , Krisztian Flautner , Trevor Mudge , David Blaauw, Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.721-725, November 10-14, 2002, San Jose, California
	Davood Shahrjerdi , Bahman Hekmatshoar , Ali Afzali-Kusha , Ali Khakifirooz, Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Po-Kuan Huang , Soheil Ghiasi, Efficient and scalable compiler-directed energy optimization for realtime applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-16, August 2007
	Na Gong , Baozeng Guo , Jianzhong Lou , Jinhui Wang, Analysis and optimization of leakage current characteristics in sub-65nm dual Vt footed domino circuits, Microelectronics Journal, v.39 n.9, p.1149-1155, September, 2008