Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation

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Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 229 - 232

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Siva Narendra	Microsystems Technology Laboratory, MIT, Cambridge, MA
Dimitri Antoniadis	Microsystems Technology Laboratory, MIT, Cambridge, MA
Vivek De	Microcomputer Research Laboratory, Intel Corp., Hillsboro, OR

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 56, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 10

	A. Keshavarzi , S. Ma , S. Narendra , B. Bloechel , K. Mistry , T. Ghani , S. Borkar , V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design, p.207-212, August 2001, Huntington Beach, California, United States
	Ashish Srivastava , Robert Bai , David Blaauw , Dennis Sylvester, Modeling and analysis of leakage power considering within-die process variations, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Siva G. Narendra, Challenges and design choices in nanoscale CMOS, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.1, p.7-49, April 2005
	James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California
	Mauro Olivieri , Giuseppe Scotti , Alessandro Trifiletti, A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.630-638, May 2005
	Murari Mani , Ashish K. Sing , Michael Orshansky, Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Dennis Sylvester , Kanak Agarwal , Saumil Shah, Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization, Integration, the VLSI Journal, v.41 n.3, p.319-339, May, 2008
	Imad A. Ferzli , Farid N. Najm, Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.770, November 09-13, 2003
	Jinseob Jeong , Seungwhun Paik , Youngsoo Shin, Statistical mixed V_t allocation of body-biased circuits for reduced leakage variation, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Maziar Goudarzi , Tohru Ishihara , Hiroto Yasuura, A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation, Microelectronics Journal, v.39 n.12, p.1797-1808, December, 2008