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Selective instruction compression for memory energy reduction in embedded systems
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents
San Diego, California, United States
Pages: 206 - 211  
Year of Publication: 1999
ISBN:1-58113-133-X
Authors
Luca Benini  Universitià di Bologna, Bologna, Italy 40136
Alberto Macii  Politecnico di Torino, Torino, Italy 10129
Enrico Macii
Massimo Poncino  Politecnico di Torino, Torino, Italy 10129
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 38,   Citation Count: 34
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E. Macii, M. Pedr&m, F. Somenli, "High-Level Power Modeling, Estimation, and Optimization," IEEE TCAD, Vol. 17, No. I1, pp. 1061-10?9, Nov. 1998.
 
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S. Wuytack, F. Catthoor, L. Nachtergaele, H. De Man, "Global Communication and Memory Optimizing Transformations for Low Power Design," IWLPD-94 pp. 203-208, Apr. 1994.
 
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S. Y. Liao, S. Devadas, K. Keutzer, "Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques," IEEE TCAD, Vol. 17, No. 7, pp. 601-608, Jul. 1996.
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Mississippi State University, Micro-Systems Prototyplng Lab., "The DLX Processor Core," http://WWW.ERC.MsState.Edu/mpl, 1998.

CITED BY  34

Collaborative Colleagues:
Luca Benini: colleagues
Alberto Macii: colleagues
Enrico Macii: colleagues
Massimo Poncino: colleagues