The design of a low energy FPGA

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The design of a low energy FPGA

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 188 - 193

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Varghese George	University of California at Berkeley, Berkeley Wireless Research Center, 2108 Allston Wy, Berkeley, CA
Hui Zhang	University of California at Berkeley, Berkeley Wireless Research Center, 2108 Allston Wy, Berkeley, CA
Jan Rabaey	University of California at Berkeley, Berkeley Wireless Research Center, 2108 Allston Wy, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 62, Citation Count: 21

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Betz, V., Rose, J. Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size in Proceedings of the IEEE 1997 Custom Integrated Circuits Conference, May 1997, 551-554.
	2	Chung, K., et al. Using Hierarchical Logic Blocks to improve the Speed of FPGAs in International Workshop on Field Programmable Logic and Applications, Oxford, UK, Sept. 1991, 4-6.
	3	Gailia, J.D., et al. A Flexible Gate Aj-my Architecture for High-Speed and High-Density Applications in IEEE J. Solid State Circuits, vol. 31, no. 3, March 1996, 430- 436.
	4	George, V. Effect of Logic Block Granularity on Interconnect Power in a Reconfigurable Logic Army. URL: http://bwrc, eec s.berkeley, edu/people/Grad_smdents/ varg~eports/CS 294/.
	5	Eric Kusse , Jan Rabaey, Low-energy embedded FPGA structures, Proceedings of the 1998 international symposium on Low power electronics and design, p.155-160, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280873]
	6	Yen-Tai Lai , Ping-Tsung Wang, Hierarchical interconnection structures for field programmable gate arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.2, p.186-196, June 1997 [doi>10.1109/92.585219]
	7	R. Llopis , M. Sachdev, Low power, testable dual edge triggered flip-flops, Proceedings of the 1996 international symposium on Low power electronics and design, p.341-345, August 12-14, 1996, Monterey, California, United States
	8	Rose, J., et al. Architecture of Field-Programmable Arrays: The Effect of Logic Block Functionality on Area Efficiency in IEEE J. Solid State Circuits, vol. 25, no. 5, Oct. 1990, 1217-1225.
	9	Rose, J., Brown, S. Flexibility of lnterconnecfion Structures for Field-Programmable Gate Arrays in IEEE J. Solid State Circuits, vol. 26, no. 3, March 1991,277- 282.
	10	Singh, S., et al. The Effect of Logic Block Architecture on FPGA Performance in IEEE J. Solid State Circuits, vol. 27, no. 3, March 1992, 281-287.
	11	Hui Zhang , Jan Rabaey, Low-swing interconnect interface circuits, Proceedings of the 1998 international symposium on Low power electronics and design, p.161-166, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280876]
	12	Xilinx XC4000XL Power Calculation. URL: http:// www. xilinx.com/xcell/x127/x127_29.pdf.
	13	Evaluating Power for Altem Devices. URL: http:// www. altem.com/documenttan/an074.pdf.

CITED BY 21

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	Juanjo Noguera , Rosa M. Badia, System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Arifur Rahman , Vijay Polavarapuv, Evaluation of low-leakage design techniques for field programmable gate arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Amit Singh , Arindam Mukherjee , Luca Macchiarulo , Malgorzata Marek-Sadowska, PITIA: an FPGA for throughput-intensive applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.354-363, June 2003
	Mihai Budiu , Girish Venkataramani , Tiberiu Chelcea , Seth Copen Goldstein, Spatial computation, ACM SIGARCH Computer Architecture News, v.32 n.5, December 2004
	Kara K. W. Poon , Steven J. E. Wilton , Andy Yan, A detailed power model for field-programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.279-302, April 2005
	Andrea Lodi , Luca Ciccarelli , Roberto Giansante, Combining low-leakage techniques for FPGA routing design, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	A. Gayasen , Y. Tsai , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , T. Tuan, Reducing leakage energy in FPGAs using region-constrained placement, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Hyung Gyu Lee , Kyungsoo Lee , Yongseok Choi , Naehyuck Chang, Cycle-Accurate Energy Measurement and Characterization of FPGAs, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.239-251, March 2005
	S. Bilavarn , E. Debes , P. Vandergheynst , J. P. Diguet, Processor Enhancements for Media Streaming Applications, Journal of VLSI Signal Processing Systems, v.41 n.2, p.225-234, September 2005
	Vijay Degalahal , Tim Tuan, Methodology for high level estimation of FPGA power consumption, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Tim Tuan , Sean Kao , Arif Rahman , Satyaki Das , Steve Trimberger, A 90nm low-power FPGA for battery-powered applications, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Julien Lamoureux , Steven J. E. Wilton, FPGA clock network architecture: flexibility vs. area and power, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Maurice Meijer , Rohini Krishnan , Martijn Bennebroek, Energy-efficient FPGA interconnect design, Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
	Philip Garcia , Katherine Compton , Michael Schulte , Emily Blem , Wenyin Fu, An overview of reconfigurable hardware in embedded systems, EURASIP Journal on Embedded Systems, v.2006 n.1, p.13-13, January 2006
	Lilian Bossuet , Guy Gogniat , Jean-Luc Philippe, Communication-oriented design space exploration for reconfigurable architectures, EURASIP Journal on Embedded Systems, v.2007 n.1, p.2-2, January 2007
	Brian Swahn , Soha Hassoun, Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.58, November 09-13, 2003
	Laura Vanzago , Bishnupriya Bhattacharya , Joel Cambonie , Luciano Lavagno, Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform, Proceedings of the conference on Design, Automation and Test in Europe, p.10662, March 03-07, 2003
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008
	Julien Lamoureux , Steven J. E. Wilton, On the trade-off between power and flexibility of FPGA clock networks, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.3, p.1-33, September 2008
	Loïc Lagadec , Bernard Pottier , Damien Picard, Toolset for nano-reconfigurable computing, Microelectronics Journal, v.40 n.4-5, p.665-672, April, 2009