Challenges in clockgating for a low power ASIC methodology

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Challenges in clockgating for a low power ASIC methodology

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 176 - 181

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

David Garrett	University of Virginia, Department of Electrical Engineering, Charlottesville, VA
Mircea Stan	University of Virginia, Department of Electrical Engineering, Charlottesville, Va
Alvar Dean	IBM Microelectronics Division, Essex Junction, VT

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 25, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. Friedman, Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press: New Jersey. 1995.
	2	J. Oh , M. Pedram, Gated clock routing minimizing the switched capacitance, Proceedings of the conference on Design, automation and test in Europe, p.692-697, February 23-26, 1998, Le Palais des Congrés de Paris, France
	3	M. Sarrfzadeh, A. Farrahi, G. Tellez, "Activity-Driven Clock Design," International Conference on Computer-Aided Design 1995.
	4	Q. Wu, M. Pedram, and X. Wu, "Clock-Gating and Its Application to Low Power Design of Sequential Circuits," IEEE Custom Integrated Circuits Conference, 1997, pp. 479-482.
	5	G. Yeap, "Low-Power Design Methodology," Kluwer Academic Publishers, 1998, p. 140-141.
	6	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	7	J. Cong, A. Kahng, G. Robins, "Matching-Based Methods for High-Performance Clock Routing", IEEE Transactions on Computer Aided Design, vol. 12., no. 8, Aug 1993, pp. 1157- 1169.
	8	T. Chao et al, "Zero-skew clock routing trees with minimum wirelength," IEEE Transactions on Circuits and Systems, Nov. 1992, p. 799-814.
	9	Qing Zhu , Wayne Wei-Ming Dai, Planar clock routing for high performance chip and package co-design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.2, p.210-226, June 1996 [doi>10.1109/92.502193]
	10	A. Kahng, C. Tsao, "Planar-DME: A Single-Layer Zero-Skew Clock Tree Router," IEEE Transactions on Computer Aided Design of lntegrated Circuits and Systems, vol. 15, no. 1, January 1996, pp. 8-19.
	11	R. Tsay, "Delay Minimization for Zero-Skew Routing." IEEE Transactions on Computer-Aided Design, February 1993.
	12	A. Vittal, M. Marek-Sadowska, "Low-Power Buffered Clock Tree Design," IEEE Transactions on Computer-Aided Design on Integrated Circuits and Systems, vol. 16, no. 9, Sept 1997, pp. 965-975.
	13	K. Carrig, et al, "A New Direction in ASIC High-Performance Clock Methodology," IEEE Custom Integrated Circuits Custom 1998, p. 593-596.

CITED BY 7

	Monica Donno , Alessandro Ivaldi , Luca Benini , Enrico Macii, Clock-tree power optimization based on RTL clock-gating, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Qi Wang , Sumit Roy, Power minimization by clock root gating, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Bipul C. Paul , Amit Agarwal , Kaushik Roy, Low-power design techniques for scaled technologies, Integration, the VLSI Journal, v.39 n.2, p.64-89, March 2006
	Pietro Babighian , Luca Benini , Enrico Macii, A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks, Proceedings of the conference on Design, automation and test in Europe, p.10500, February 16-20, 2004
	Chia-Ming Chang , Shih-Hsu Huang , Yuan-Kai Ho , Jia-Zong Lin , Hsin-Po Wang , Yu-Sheng Lu, Type-matching clock tree for zero skew clock gating, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Wei-Chung Chao , Wai-Kei Mak, Low-power gated and buffered clock network construction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-20, January 2008