VIP—an input pattern generator for indentifying critical voltage drop for deep sub-micron designs

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VIP—an input pattern generator for indentifying critical voltage drop for deep sub-micron designs

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 156 - 161

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Yi-Min Jiang	Dept. of Electrical & Computer Engineering, University of California, Santa Barbara, CA
Tak K. Young	Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA
Kwang-Ting Cheng	Dept. of Electrical & Computer Engineering, University of California, Santa Barbara, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A.-C. Deng, "Power Analysis for CMOS/BiCMOS Circuits," International Symposium on Low-Power Electronics and Design (ISLPED), pp. 3-8, 1994.
	2	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, K2: an estimator for peak sustainable power of VLSI circuits, Proceedings of the 1997 international symposium on Low power electronics and design, p.178-183, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263321]
	3	David E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
	4	Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm,'' Proc. of lEEE Custom Integrated Circuits Conference, pp. 135-138, May 1997.
	5	Yi-Min Jiang , Kwang-Ting Cheng , An-Chang Deng, Estimation of maximum power supply noise for deep sub-micron designs, Proceedings of the 1998 international symposium on Low power electronics and design, p.233-238, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280915]
	6	B. L. Miller and D. E. Goldberg, "Genetic Algorithms, Tournament Selection, and the Effects of Noise;' Complex Systems, pp. 193-212, June 1995.
	7	Christos H. Papadimitriou , Kenneth Steiglitz, Combinatorial optimization: algorithms and complexity, Prentice-Hall, Inc., Upper Saddle River, NJ, 1982
	8	SYNOPSYS, "Arcadia User Guide," August 1998.
	9	SYNOPSYS, "PowerMill User Guide", August 1998.
	10	SYNOPSY S, "RailMill User Guide,' August 1998.
	11	K. Yoshida, "Speed Up of An Evaluation Speed 5-15 Times Faster by Using Hierarchical Power Supply Network" NTT LSI Lab.

CITED BY 5

	Rajendran Panda , David Blaauw , Rajat Chaudhry , Vladimir Zolotov , Brian Young , Ravi Ramaraju, Model and analysis for combined package and on-chip power grid simulation, Proceedings of the 2000 international symposium on Low power electronics and design, p.179-184, July 25-27, 2000, Rapallo, Italy
	Min Zhao , Rajendran V. Panda , Sachin S. Sapatnekar , Tim Edwards , Rajat Chaudhry , David Blaauw, Hierarchical analysis of power distribution networks, Proceedings of the 37th conference on Design automation, p.150-155, June 05-09, 2000, Los Angeles, California, United States
	Sanjay Pant , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda, A stochastic approach To power grid analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Yi Zhao , Sujit Dey , Li Chen, Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.746-755, July 2004
	Sanjay Pant , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda, Vectorless Analysis of Supply Noise Induced Delay Variation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.184, November 09-13, 2003