Monotonic static CMOS and dual-VT technology

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Monotonic static CMOS and dual-VT technology

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 151 - 155

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Tyler Thorp	Department of Electrical Engineering, University of Washington, Seattle, WA
Gin Yee	Department of Electrical Engineering, University of Washington, Seattle, WA
Carl Sechen	Department of Electrical Engineering, University of Washington, Seattle, WA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 18, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Dunning, Transistor-Level Sizing and Timing Verification of Domino Circuits in the Power PC(TM) Microprocessor, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.143, October 12-15, 1997
	2	D. Harris and M. Horowitz, "Skew-tolerant domino circuits;' IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 1702-1711, 1997.
	3	F. Klass, et. al., "A new family of semi-dynamic and dynamic flipflops with embedded logic for high-performance microprocessors;' IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 712-717, 1999.
	4	C. Lee and E. Szeto, "Zipper CMOS;' IEEE Circuits and Devices Magazine, pp. 10-16, May 1986.
	5	S. Mutoh, et. al., "I-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS" IEEE J Solid-State Circuits, vol. 30, no. 8, pp. 847-854, 1995.
	6	M. Prasad, D. Kirkpatrick, R. Brayton, and A. Sangiovanni-Vincentelli, "Domino logic synthesis and technology mapping," Proc. Int. Workshop on Logic Synthesis, vol. 1, 1997.
	7	Ruchir Puri , Andrew Bjorksten , Thomas E. Rosser, Logic optimization by output phase assignment in dynamic logic synthesis, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.2-7, November 10-14, 1996, San Jose, California, United States
	8	E. Sentovich, et. al., "SIS: a system for sequential circuit synthesis," Technical Report UCB/ERL M92/41, University of California, Berkeley, CA, May 1992.
	9	Tyler Thorp , Gin Yee , Carl Sechen, Domino logic synthesis using complex static gates, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.242-247, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288620]
	10	Qi Wang , Sarma B. K. Vrudhula, Static power optimization of deep submicron CMOS circuits for dual VT technology, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.490-496, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289076]
	11	Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits, Proceedings of the 35th annual conference on Design automation, p.489-494, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277179]
	12	Gin Yee , Carl Sechen, Clock-Delayed Domino for Adder and Combinational Logic Desig, Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors, p.332, October 07-09, 1996

CITED BY 5

	Tyler J. Thorp , Gin S. Yee , Carl M. Sechen, Design and synthesis of dynamic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.141-149, February 2003
	Chulwoo Kim , Ki-Wook Kim , Sung-Mo Kang, Energy-efficient skewed static logic with dual Vt: design and synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.64-70, February 2003
	Alexandre Solomatnikov , Dinesh Somasekhar , Naran Sirisantana , Kaushik Roy, Skewed CMOS: noise-tolerant high-performance low-power static circuit family, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.469-476, August 2002
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Aiqun Cao , Naran Sirisantana , Cheng-Kok Koh , Kaushik Roy, Synthesis of skewed logic circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.205-228, April 2005