| Clock distribution using multiple voltages |
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International Symposium on Low Power Electronics and Design
archive
Proceedings of the 1999 international symposium on Low power electronics and design
table of contents
San Diego, California, United States
Pages: 145 - 150
Year of Publication: 1999
ISBN:1-58113-133-X
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Authors
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Jatuchai Pangjun
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Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
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Sachin S. Sapatnekar
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Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 12, Citation Count: 4
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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K.D. Boese and A. B. Kahng, "Zero-skew clock routing trees with minimum wire length," in Proceedings of the IEEE International Conference on ASIC, pp. 1.1. t-1.1.5, 1992.
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2
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T.-H. Chao , J.-M. Ho , Y.-C. Hsu, Zero skew clock net routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.518-523, June 08-12, 1992, Anaheim, California, United States
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Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123406]
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6
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Andrew Kahng , Jason Cong , Gabriel Robins, High-performance clock routing based on recursive geometric matching, Proceedings of the 28th conference on ACM/IEEE design automation, p.322-327, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127688]
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7
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R. S. Tsay, "Exact zero skew clock net routing," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 242-249, Feb. 1993.
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Mutsunori Igarashi , Kimiyoshi Usami , Kazutaka Nogami , Fumihiro Minami , Yukio Kawasaki , Takahiro Aoki , Midori Takano , Chiharo Mizuno , Takashi Ishikawa , Masahiro Kanazawa , Shinji Sonoda , Makoto Ichida , Naoyuki Hatanaka, A low-power design method using multiple supply voltages, Proceedings of the 1997 international symposium on Low power electronics and design, p.36-41, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263279]
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Semiconductor Industry Association, National Technology Roadmap for Semiconductors. 1997.
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L.P.P.P. van Ginneken, "Buffer placement in distributed RC- tree networks for minimal Elmore delay," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865-868, 1990.
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H. I. Hanafi, R. H. Dennard, and C. L. Chen, "Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance," IEEE Journal of Solid- State Circuits, vol. 27, pp. 783-790, May 1992.
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17
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M. Bazes, "Two novel fully complementary self-biased CMOS differential amplifiers," IEEE Journal of Solid-State Circuits, vol. 26, pp. 165-168, Feb. 1991.
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18
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J. Cong, "Challenges and opportunities for design innovations in nanometer technologies," tech. rep., Semiconductor Research Corporation, Research Triangle Park, NC, 1997.
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CITED BY 4
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Monica Donno , Alessandro Ivaldi , Luca Benini , Enrico Macii, Clock-tree power optimization based on RTL clock-gating, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Yongseok Cheon , Pei-Hsin Ho , Andrew B. Kahng , Sherief Reda , Qinke Wang, Power-aware placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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