Low power synthesis of dual threshold voltage CMOS VLSI circuits

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Low power synthesis of dual threshold voltage CMOS VLSI circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 139 - 144

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Vijay Sundararajan	Dept. of ECE University of Minnesota, Minneapolis, MN
Keshab K. Parhi	Dept. of ECE University of Minnesota, Minneapolis, MN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 28, Citation Count: 27

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 27

	J. Adam Butts , Gurindar S. Sohi, A static power model for architects, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.191-201, December 2000, Monterey, California, United States
	Luca Benini , Giovanni De Micheli, Logic synthesis for low power, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Chulwoo Kim , Ki-Wook Kim , Sung-Mo Kang, Energy-efficient skewed static logic with dual Vt: design and synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.64-70, February 2003
	Mahesh Ketkar , Sachin S. Sapatnekar, Standby power optimization via transistor sizing and dual threshold voltage assignment, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.375-378, November 10-14, 2002, San Jose, California
	Ankur Srivastava, Simultaneous Vt selection and assignment for leakage optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Narender Hanchate , Nagarajan Ranganathan, LECTOR: a technique for leakage reduction in CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.196-205, February 2004
	Puneet Gupta , Andrew B. Kahng , Puneet Sharma , Dennis Sylvester, Selective gate-length biasing for cost-effective runtime leakage control, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Yen-Te Ho , Ting-Ting Hwang, Low power design using dual threshold voltage, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.205-208, January 27-30, 2004, Yokohama, Japan
	Frank Sill , Frank Grassert , Dirk Timmermann, Low power gate-level design with mixed-V_th (MVT) techniques, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Azadeh Davoodi , Ankur Srivastava, Probabilistic dual-Vth leakage optimization under variability, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Frank Sill , Frank Grassert , Dirk Timmermann, Total leakage power optimization with improved mixed gates, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Low-power fanout optimization using multiple threshold voltage inverters, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Azadeh Davoodi , Ankur Srivastava, Probabilistic evaluation of solutions in variability-driven optimization, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Yu-Hui Huang , Po-Yuan Chen , TingTing Hwang, Switching-activity driven gate sizing and Vth assignment for low power design, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Chang-woo Kang , Massoud Pedram, Technology mapping for low leakage power and high speed with hot-carrier effect consideration, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Frank Sill , Jiaixi You , Dirk Timmermann, Design of mixed gates for leakage reduction, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Jeegar Tilak Shah , Marius Evers , Jeff Trull , Alper Halbutogullari, Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Ralf Salomon , Frank Sill , Dirk Timmermann, Minimizing leakage: what if every gate could have its individual threshold voltage?, Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications, p.492-497, February 12-14, 2007, Innsbruck, Austria
	Ralf Salomon , Frank Sill, High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.5-6, p.321-327, May, 2007
	S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Blaauw , V. Zolotov, Discrete Vt assignment and gate sizing using a self-snapping continuous formulation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.705-712, November 06-10, 2005, San Jose, CA
	Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Hsien-Hsin Sean Lee, Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.693, November 09-13, 2003
	Debasis Samanta , Ajit Pal, Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.193, January 07-11, 2002
	Tai-Hsuan Wu , Lin Xie , Azadeh Davoodi, A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Yifang Liu , Jiang Hu, A new algorithm for simultaneous gate sizing and threshold voltage assignment, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA