Efficient switching activity computation during high-level synthesis of control-dominated designs

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Efficient switching activity computation during high-level synthesis of control-dominated designs

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 127 - 132

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

A. Bogliolo	DEIS - Universitá di Bologna, Bologna, Italy
L. Benini	DEIS - Universitá di Bologna, Bologna, Italy
B. Riccó	DEIS - Universitá di Bologna, Bologna, Italy
G. De Micheli	CSL - Stanford University, Stanford, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	2	Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
	3	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
	4	Subodh Gupta , Farid N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual conference on Design automation, p.365-370, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266171]
	5	A. Chandrakasan et al., "Optimizing Power Using Transformations," IEEE Trans. on CAD, vol. 14, no. 1, pp. 12-31, Jan. 1995.
	6	Nand Kumar , Srinivas Katkoori , Leo Rader , Ranga Vemuri, Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems, IEEE Design & Test, v.12 n.3, p.70-84, September 1995 [doi>10.1109/MDT.1995.466383]
	7	Raul San Martin , John P. Knight, Optimizing Power in ASIC Behavioral Synthesis, IEEE Design & Test, v.13 n.2, p.58-70, June 1996 [doi>10.1109/54.500201]
	8	A. Raghunathanet al., "SCALP: An Iterative-Improvement- Based Low-Power Data Path Synthesis System," IEEE Trans. on CAD, vol. 16, no. 11, pp. 1260-1277, Nov. 1997.
	9	J. Chang et al., "Module Assignment for Low Power," EDAC-96, pp. 16-376-81, 1996.
	10	J. E. Crenshaw , M. Sarrafzadeh, Accurate high level datapath power estimation, Proceedings of the 1997 European conference on Design and Test, p.590, March 17-20, 1997
	11	K. S. Khouri , G. Lakshminarayana , N. K. Jha, IMPACT: a high-level synthesis system for low power control-flow intensive circuits, Proceedings of the conference on Design, automation and test in Europe, p.848-854, February 23-26, 1998, Le Palais des Congrés de Paris, France
	12	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Fast high-level power estimation for control-flow intensive design, Proceedings of the 1998 international symposium on Low power electronics and design, p.299-304, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280941]
	13	Alessandro Bogiolo , Luca Benini , Bruno Riccò, Power estimation of cell-based CMOS circuits, Proceedings of the 33rd annual conference on Design automation, p.433-438, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240601]

CITED BY 2

	Deming Chen , Jason Cong , Yiping Fan, Low-power high-level synthesis for FPGA architectures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Deming Chen , Jason Cong , Junjuan Xu, Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.362-386, April 2006