Ultra-low power digital subthreshold logic circuits

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Ultra-low power digital subthreshold logic circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 94 - 96

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Hendrawan Soeleman	Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Kaushik Roy	Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 29, Downloads (12 Months): 154, Citation Count: 15

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	9	William C. Athas , Lars J. Svensson , Jeffrey G. Koller , Nestoras Tzartzanis , Eric Ying-Chin Chou, Low-power digital systems based on adiabatic-switching principles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.398-407, Dec. 1994 [doi>10.1109/92.335009]
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CITED BY 15

	Hendrawan Soeleman , Kaushik Roy , Bipul Paul, Robust ultra-low power sub-threshold DTMOS logic, Proceedings of the 2000 international symposium on Low power electronics and design, p.25-30, July 25-27, 2000, Rapallo, Italy
	Hyung-il Kim , Kaushik Roy, Ultra-low power DLMS adaptive filter for hearing aid applications, Proceedings of the 2001 international symposium on Low power electronics and design, p.352-357, August 2001, Huntington Beach, California, United States
	Luiz Alberto P. Melek , Márcio C. Schneider , Carlos Galup-Montoro, Body-bias compensation technique for SubThreshold CMOS static logic gates, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Bo Zhai , David Blaauw , Dennis Sylvester , Krisztian Flautner, Theoretical and practical limits of dynamic voltage scaling, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Nikhil Jayakumar , Sunil P. Khatri, A variation tolerant subthreshold design approach, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Bo Zhai , David Blaauw , Dennis Sylvester , Krisztian Flautner, The limit of dynamic voltage scaling and insomniac dynamic voltage scaling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1239-1252, November 2005
	Nikhil Jayakumar , Rajesh Garg , Bruce Gamache , Sunil P. Khatri, A PLA based asynchronous micropipelining approach for subthreshold circuit design, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Joseph F. Ryan , Jiajing Wang , Benton H. Calhoun, Analyzing and modeling process balance for sub-threshold circuit design, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Myeong-Eun Hwang , Tamer Cakici , Kaushik Roy, Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Jaydeep P. Kulkarni , Keejong Kim , Kaushik Roy, A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Jaydeep P. Kulkarni , Keejong Kim , Sang Phill Park , Kaushik Roy, Process variation tolerant SRAM array for ultra low voltage applications, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Jing Li , Aditya Bansal , Swarop Ghosh , Kaushik Roy, An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.4 n.3, p.1-19, August 2008
	Francesco Zanini , David Atienza , Giovanni De Micheli, A control theory approach for thermal balancing of MPSoC, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Sohan Purohit , Martin Margala , Marco Lanuzza , Pasquale Corsonello, New performance/power/area efficient, reliable full adder design, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Ramesh Vaddi , S. Dasgupta , R. P. Agarwal, Device and circuit design challenges in the digital subthreshold region for ultralow-power applications, VLSI Design, 2009, p.1-14, January 2009