Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

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Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 70 - 75

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Kanad Ghose	Department of Computer Science, State University of New York, Binghamton, NY
Milind B. Kamble	Hewlett-Packard VLSI Technology Labratory, Fort Collins, CO and Department of Computer Science, State University of New York, Binghamton, NY

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 83, Citation Count: 68

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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