Energy-efficient signal processing via algorithmic noise-tolerance

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Energy-efficient signal processing via algorithmic noise-tolerance

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 30 - 35

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Rajamohana Hegde	ECE Department/Coordinated Science Laboratory, University of Illinois, Urbana, IL
Naresh R. Shanbhag	ECE Department/Coordinated Science Laboratory, University of Illinois, Urbana, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 43, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Iman and M. Pedram, "An approach for multi-level logic optimization targeting low power," IEEE Trans. on Computer Aided Design, Vol. 15, No. 8 (1996), pages 889-901.
	2	R. Gonzalez, et. al., "Supply and threshold voltage scaling for low power CMOS," iEEE Journal of Solid State Circuits, vol. 32, No. 8, Aug. 1997.
	3	Vadim Gutnik , Anantha P. Chandrakasan, Embedded power supply for low-power DSP, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.425-435, Dec. 1997 [doi>10.1109/92.645069]
	4	R. Hegde and N. R. Shanbhag, "A Low-power phase splitting passband equalizer," IEEE Trans. on Signal Processing, vol. 47, no. 3, March 1999.
	5	A. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the iEEE, vol. 83, no. 4, pp. 498-523, April 1995.
	6	Phillip J. Restle , Joel Phillips , Ibrahim Elfadel, Interconnect in high speed designs: problems, methodologies and tools, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.4, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288551]
	7	Kenneth L. Shepard , Vinod Narayanan, Noise in deep submicron digital design, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.524-531, November 10-14, 1996, San Jose, California, United States
	8	N. R. Shanbhag, "A mathematical basis for power-reduction in digital VLSI systems", IEEE Trans. on Circuits and Systems, Part II, vol. 44, no. 11, pp. 935-951, Nov. 1997.
	9	Rajamohana Hegde , Naresh R. Shanbhag, Energy-efficiency in presence of deep submicron noise, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.228-234, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288618]
	10	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	11	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288614]
	12	M. D. Ercegovac and T. Lang, "Low-Power Accumulator (Correlator)," in proc. International symposium on Low- Power Electronic Design (ISLPED),san Francisco, CA, 1995, pp. 30-31.
	13	John G. Proakis , Dimitris G. Manolakis, Digital signal processing (3rd ed.): principles, algorithms, and applications, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	14	Michael G. Xakellis , Farid N. Najm, Statistical estimation of the switching activity in digital circuits, Proceedings of the 31st annual conference on Design automation, p.728-733, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196628]

CITED BY 5

	Naresh Shanbhag , K. Soumyanath , Samuel Martin, Reliable low-power design in the presence of deep submicron noise (embedded tutorial session), Proceedings of the 2000 international symposium on Low power electronics and design, p.295-302, July 25-27, 2000, Rapallo, Italy
	Lei Wang , Naresh Shanbhag, Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers, Proceedings of the 2001 international symposium on Low power electronics and design, p.334-339, August 2001, Huntington Beach, California, United States
	Byonghyo Shim , Srinivasa R. Sridhara , Naresh R. Shanbhag, Reliable low-power digital signal processing via reduced precision redundancy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.5, p.497-510, May 2004
	Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev Rao , Toan Pham , Conrad Ziesler , David Blaauw , Todd Austin , Krisztian Flautner , Trevor Mudge, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.7, December 03-05, 2003
	Yu-Shih Su , Po-Hsien Chang , Shih-Chieh Chang , Tingting Hwang, Synthesis of a novel timing-error detection architecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-14, January 2008