IC test using the energy consumption ratio

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IC test using the energy consumption ratio

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 976 - 981

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Wanli Jiang	Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
Bapiraju Vinnakota	Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sreejit Chakravarty , Paul J. Thadikaran, Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits, IEEE Transactions on Computers, v.45 n.10, p.1131-1140, October 1996 [doi>10.1109/12.543707]
	2	Tzuhao Chen , Ibrahim N. Hajj , Elizabeth M. Rudnick , Janak H. Patel, An Efficient IDDQ Test Generation Scheme for Bridging Faults in CMOS Digital Circuits, Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96), p.74, October 24-25, 1996
	3	Jonathan T. -Y. Chang , Edward J. McCluskey, Detecting Bridging Faults in Dynamic CMOS Circuits, Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97), p.106, November 05-06, 1997
	4	M. Dalpasso, M. Favalli, and E Olivo, "I99Q Test Invalidation by Break faults," Electronics Letters, Vol. 32, No. 11, pp. 994-995, 1996.
	5	T. W. Williams , R. Kapur , M. R. Mercer , R. H. Dennard , W. Maly, Iddq Testing for High Performance CMOS - The Next Ten Years, Proceedings of the 1996 European conference on Design and Test, p.578, March 11-14, 1996
	6	M. Sachdev, Deep Sub-Micron IDDQ Testing: Issues and Solutions, Proceedings of the 1997 European conference on Design and Test, p.271, March 17-20, 1997
	7	J. Beasely, H. Ramamurthy, J. Ramirez-Angulo, and M. Deyong, "Idd Pulse Response Testing: A Unified Approach to Testing Digital and Analogue ICs," Electronics Letters, pp. 2101-2103, Nov. 25 1993.
	8	Shyang-Tai Su , Rafic Z. Makki , Troy Nagle, Transient power supply current monitoring—a new test method for CMOS VLSI circuits, Journal of Electronic Testing: Theory and Applications, v.6 n.1, p.23-43, Feb. 1995 [doi>10.1007/BF00993128]
	9	J. A. Segura , M. Roca , D. Mateo , A. Rubio, An approach to dynamic power consumption current testing of CMOS ICs, Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), p.95, April 30-May 03, 1995
	10	James F. Plusquellic , Donald M. Chiarulli , Steven P. Levitan, Digital Integrated Circuit Testing using Transient Signal Analysis, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.481-490, October 20-25, 1996
	11	A. Walker , P. K. Lala, An Approach For Detecting Bridging Fault-Induced Delay Faults In Static CMOS Circuits Using Dynamic Power Supply Current Monitoring, Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97), p.73, November 05-06, 1997
	12	Y. Min, Z. Zhao, and Z. Li, "I99T Testing," Proc. Asian Test Sympos., pp. 378-382, 1997.
	13	B. Vinnakota, Monitoring power dissipation for fault detection, Proceedings of the 14th IEEE VLSI Test Symposium (VTS '96), p.483, April 28-May 01, 1996
	14	Bapiraju Vinnakota , Wanli Jiang , Dechang Sun, Process-tolerant test with energy consumption ratio, Proceedings of the 1998 IEEE International Test Conference, p.1027-1036, October 18-22, 1998
	15	Jiing-Yuan Lin , Tai-Chien Liu , Wen-Zen Shen, A cell-based power estimation in CMOS combinational circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.304-309, November 06-10, 1994, San Jose, California, United States
	16	H. Satin, and A. McNelly, "A Power Modeling and Characterization Method for Logic Simulation," Proc. IEEE Custom Integrated Circuits Conf., pp.363-366, 1995.
	17	http://www.mosis.org, Mosis Web Site.

CITED BY 5

	Shih-Yu Yang , Christos A. Papachristou , Massood Tabib-Azar, Improving bus test via IDDT and boundary scan, Proceedings of the 38th conference on Design automation, p.307-312, June 2001, Las Vegas, Nevada, United States
	Xiaoyun Sun , Seonki Kim , Bapiraju Vinnakota, Crosstalk fault detection by dynamic Idd, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Bapiraju Vinnakota, Deep submicron defect detection with the energy consumption ratio, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.467-470, November 07-11, 1999, San Jose, California, United States
	Swarup Bhunia , Kaushik Roy, A novel wavelet transform-based transient current analysis for fault detection and localization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.4, p.503-507, April 2005
	Ali Chehab , Saurabh Patel , Rafic Makki, Scaling of iDDT Test Methods for Random Logic Circuits, Journal of Electronic Testing: Theory and Applications, v.22 n.1, p.11-22, February 2006