A methodology for accurate performance evaluation in architecture exploration

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A methodology for accurate performance evaluation in architecture exploration

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 927 - 932

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

George Hadjiyiannis	Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, Cambridge, MA
Pietro Russo	Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, Cambridge, MA
Srinivas Devadas	Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, Cambridge, MA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 37, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	George Hadjiyiannis , Silvina Hanono , Srinivas Devadas, ISDL: an instruction set description language for retargetability, Proceedings of the 34th annual conference on Design automation, p.299-302, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266108]
	2	Silvina Hanono , Srinivas Devadas, Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator, Proceedings of the 35th annual conference on Design automation, p.510-515, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277184]
	3	G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. Technical report, Massachusetts Institute of Technology, 1996. (http://www.ee.princeton.edu/spam/pubs/ISDL-TR.html).
	4	G. I. Hadjiyiannis. ISDL: Instruction Set Description Language - Version 1.0. MIT Laboratory for Computer Science, July 1998. (http://www.caa.lcs.mit.edu/~ghi/PostScript/ isdl manual.ps).
	5	Peter Marwedel, The mimola design system: Tools for the design of digital processors, Proceedings of the 21st conference on Design automation, p.587-593, June 25-27, 1984, Albuquerque, New Mexico, United States
	6	G. Zimmermann, The MIMOLA design system a computer aided digital processor design method, Proceedings of the 16th Conference on Design automation, p.53-58, June 25-27, 1979, San Diego, CA, United States
	7	A. Fauth, J. Van Praet, and M. Freericks. Describing Instruction Sets Using UML (Extended Version). Technical report, Technische Universitat Berlin and IMEC, Berlin (Germany)/Leuven (Belgium), 1995.
	8	D. Lanneer et al. CHESS: Retargetable Code Generation for Embedded DSP Processors. In Code Generation for Embed-ded Processors. Kluwer Academic Publishers, 1995.
	9	Mark R. Hartoog , James A. Rowson , Prakash D. Reddy , Soumya Desai , Douglas D. Dunlop , Edwin A. Harcourt , Neeti Khullar, Generation of software tools from processor descriptions for hardware/software codesign, Proceedings of the 34th annual conference on Design automation, p.303-306, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266110]
	10	V. Zivojnovic, S. Pees, and H. Meyr. LISA - Machine Description Language and Generic Machine Model for HW/SW Co-Design. In Proceedings of 1996 IEEE Workshop on VLSI Signal Processing, 1996.
	11	J. C. Gyllenhaal, W. W. Hwu, and B. R. Rau. HMDES Version 2.0 Specification. Technical Report IMPACT-96-3, University of Illinois, Urbana, 1996.
	12	V. Kathail, M. S. Schlansker, and B. R. Rau. HPL PlayDoh Architecture Specification: Version 1.0. Technical Report HPL-93- 80, Hewlett-Packard Laboratories, 1994.

CITED BY 12

	Gunnar Braun , Andreas Hoffmann , Achim Nohl , Heinrich Meyr, Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Henrik Theiling, Generating Decision Trees for Decoding Binaries, ACM SIGPLAN Notices, v.36 n.8, p.112-120, Aug. 2001
	Wei Qin , Sharad Malik, Automated synthesis of efficient binary decoders for retargetable software toolkits, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Tilman Glökler , Andreas Hoffmann , Heinrich Meyr, Methodical Low-Power ASIP Design Space Exploration, Journal of VLSI Signal Processing Systems, v.33 n.3, p.229-246, March 2003
	Reinaldo A. Bergamaschi , Youngsoo Shin , Nagu Dhanwada , Subhrajit Bhattacharya , William E. Dougherty , Indira Nair , John Darringer , Sarala Paliwal, SEAS: a system for early analysis of SoCs, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
	Timothy Sherwood , Mark Oskin , Brad Calder, Balancing design options with Sherpa, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	In-Cheol Park , Sehyeon Kang , Yongseok Yi, Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.138, November 09-13, 2003
	Sungpack Hong , Sungjoo Yoo , Sheayun Lee , Sangwoo Lee , Hye Jeong Nam , Bum-Seok Yoo , Jaehyung Hwang , Donghyun Song , Janghwan Kim , Jeongeun Kim , HoonSang Jin , Kyu-Myung Choi , Jeong-Taek Kong , SooKwan Eo, Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Prabhat Mishra , Aviral Shrivastava , Nikil Dutt, Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.626-658, July 2006
	Newton Cheung , Jorg Henkel , Sri Parameswaran, Rapid Configuration and Instruction Selection for an ASIP: A Case Study, Proceedings of the conference on Design, Automation and Test in Europe, p.10802, March 03-07, 2003
	Oliver Schliebusch , Andreas Hoffmann , Achim Nohl , Gunnar Braun , Heinrich Meyr, Architecture Implementation Using the Machine Description Language LISA, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.239, January 07-11, 2002
	Shail Aditya , B. Ramakrishna Rau , Vinod Kathail, Automatic Architectural Synthesis of VLIW and EPIC Processors, Proceedings of the 12th international symposium on System synthesis, p.107, November 01-04, 1999