On-chip inductance issues in multiconductor systems

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On-chip inductance issues in multiconductor systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 921 - 926

Year of Publication: 1999

ISBN:1-58133-109-7

Author

Shannon V. Morton

Alpha Development Group, Compaq Computer Corporation, Shrewsbury, MA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Fair, D. Bailey, "Clocking Design and Analysis for a 600 MHz Alpha Microprocessor", ISSCC Digest of Technical Papers, Feb 1998, pp. 398-399.
	2	P. Gronowski, W. Bowhill, R. Preston, M. Gowan, R. Allmon, "High-Performance Microprocessor Design", IEEE Journal of Solid-State Circuits, May 1998, pp. 676-686.
	3	Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Figures of merit to characterize the importance of on-chip inductance, Proceedings of the 35th annual conference on Design automation, p.560-565, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277193]
	4	B. A. Gieseke et al., "A 600MHz Superscalar RISC Microprocessor with Out-Of-Order Execution", ISSCC Digest of Technical Papers, Feb 1997, pp. 176-177.

CITED BY 7

	Kaustav Banerjee , Amit Mehrotra, Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects, Proceedings of the 38th conference on Design automation, p.798-803, June 2001, Las Vegas, Nevada, United States
	T. Chen, On the impact of on-chip inductance on signal nets under the influence of power grid noise, Proceedings of the conference on Design, automation and test in Europe, p.451-459, March 2001, Munich, Germany
	David Blaauw , Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Junfeng Wang, On-chip inductance modeling, Proceedings of the 10th Great Lakes symposium on VLSI, p.75-80, March 02-04, 2000, Chicago, Illinois, United States
	Norman Chang , Shen Lin , Lei He , O. Sam Nakagawa , Weize Xie, Clocktree RLC extraction with efficient inductance modeling, Proceedings of the conference on Design, automation and test in Europe, p.522-526, March 27-30, 2000, Paris, France
	Tao Lin , Lawrence T. Pileggi, Throughput-driven IC communication fabric synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.274-279, November 10-14, 2002, San Jose, California
	Takashi Sato , Hiroo Masuda, Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.209-217, March 2005
	M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.225-248, June 2002