IC analyses including extracted inductance models

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IC analyses including extracted inductance models

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 915 - 920

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Michael W. Beattie	Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, PA
Lawrence T. Pileggi	Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 22, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kevin J. Kerns , Ivan L. Wemple , Andrew T. Yang, Stable and efficient reduction of substrate model networks using congruence transforms, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.207-214, November 05-09, 1995, San Jose, California, United States
	2	Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States
	3	L. Pillage, R. Rohrer, Asymptotic Waveform Evaluation for Timing Analysis, IEEE. Trans. Computer-Aided Design, 9, No. 4 (Apr. 1990).
	4	L. Miguel Silveira , Mattan Kamon , Jacob White, Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.376-380, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217558]
	5	A. Deutsch , G. V. Kopcsay , B. J. Rubin , C. W. Surovic , L. M. Terman , R. P. Dunne, Jr. , T. A. Gallo , R. H. Dennard, Modeling and characterization of long on-chip interconnections for high-performance microprocessors, IBM Journal of Research and Development, v.39 n.5, p.547-567, Sept. 1995
	6	F. Grover, Inductance Calculations, Dover Publications, New York (1946).
	7	M. Kamon, M. Tsuk, J. White, FASTHENRY: A Multipole Accelerated 3-D Inductance Extraction Program, IEEE Trans. Microwave Theory and Techniques, 42, No. 9, pp. 1750-1758 (Sept. 1994).
	8	Byron Krauter , Lawrence T. Pileggi, Generating sparse partial inductance matrices with guaranteed stability, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.45-52, November 05-09, 1995, San Jose, California, United States
	9	M. Beattie, L. Alatan, L. Pileggi, Equipotential Shells for Efficient Partial Inductance Extraction, Proc. 1998 IEDM (Dec. 1998).
	10	E. Rosa, The Self and Mutual Inductance of Linear Conductors, Bulletin of the National Bureau of Standards, 4, pp. 301-344 (1908).
	11	A. Ruehli, Inductance Calculations in a Complex Integrated Circuit Environment, IBM J. Res. Dev., 16, No. 5, pg. 470-481 (Sept. 1972).
	12	W. Weeks, L. Wu, M. McAllister, A. Singh, Resistive and Inductive Skin Effect in Rectangular Conductors, IBM J. Res. Dev., 23, No. 6, pg. 652-660 (Nov. 1979).
	13	F. Dartu, CMOS gate delay models for general RLC loading, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.224, October 12-15, 1997
	14	M. Kamon, N. Marques, L. Silveira, J. White, Generating Reduced Order Models via PEEC for Capturing Skin and Proximity Effects, Proc. 6 th Meeting on Electr. Perform. of Electr. Packaging, San Jose (Nov. 1997).
	15	D. Bailey, B. Benschneider, Clocking Design and Analysis for a 600-MHz Alpha Microprocessor, IEEE J. Solid-State Circuits, 33, No. 11 (Nov. 1998).

CITED BY 13

	Kaustav Banerjee , Amit Mehrotra, Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects, Proceedings of the 38th conference on Design automation, p.798-803, June 2001, Las Vegas, Nevada, United States
	T. Chen, On the impact of on-chip inductance on signal nets under the influence of power grid noise, Proceedings of the conference on Design, automation and test in Europe, p.451-459, March 2001, Munich, Germany
	Michael W. Beattie , Lawrence T. Pileggi, Modeling magnetic coupling for on-chip interconnect, Proceedings of the 38th conference on Design automation, p.335-340, June 2001, Las Vegas, Nevada, United States
	Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States
	M. Beattle , L. Pileggi, Efficient inductance extraction via windowing, Proceedings of the conference on Design, automation and test in Europe, p.430-436, March 2001, Munich, Germany
	Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States
	Mattan Kamon , Steve McCormick , Ken Sheperd, Interconnect parasitic extraction in the digital IC design methodology, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.223-231, November 07-11, 1999, San Jose, California, United States
	Jun Chen , Lei He, Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Guoan Zhong , Cheng Kok Koh , Kaushik Roy, A twisted-bundle layout structure for minimizing inductive coupling noise, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	James D. Z. Ma , Lei He, Formulae and applications of interconnect estimation considering shield insertion and net ordering, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Michael Beattie , Satrajit Gupta , Lawrence Pileggi, Hierarchical interconnect circuit models, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Jun Chen , Lei He, Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Dipanjan Gope , Albert E. Ruehli , Vikram Jandhyala, Speeding Up PEEC partial inductance computations using a QR-based algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.1, p.60-68, January 2007