On thermal effects in deep sub-micron VLSI interconnects

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

On thermal effects in deep sub-micron VLSI interconnects

Full text

Pdf (932 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 885 - 891

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Kaustav Banerjee	Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Amit Mehrotra	Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Alberto Sangiovanni-Vincentelli	Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Chenming Hu	Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 19, Downloads (12 Months): 88, Citation Count: 34

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/309847.310093 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. R. Barrett, "Microprocessor evolution and technology impact," Syrup. VI_SI Technol, Dig. Tech. Paperr, 1993, pp. 7-10.
	2	T. Makimoto, "Market and technology trends in the nomadic age," Syrup. I/kfl Technol, Dig. Tech. Papers, 1996, pp. 6-9.
	3	R. Whittier, "Push/Pull: PC technology/end user demand," Syrup. 1/7_~I Technol, Dig. Tecb. Papers, 1996, pp. 2-5.
	4	R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bassous, and A. R. LeBank, "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Soh'd-State Circuits, Vol. SC-9, pp. 256-268, 1974.
	5	P. K. Chatterjee, W. R. Hunter, A. Amerasekera, S. Aur, C. Duvvury, P. E. Nicollian, L. M. Yang, and P. Yang, "Trends for deep submicron VLSI and their implications for reliability," Proc/RPS, 1995, pp. 1-11.
	6	J. R. Black, "Electromigrafion - A brief survey and some recent results," IEEE Trans. Electron Devices, vol. ED-16, pp. 338-347, 1969.
	7	B. K. Liew, N. W. Cheung, and C. Hu, "Projecting interconnect electromigration lifetime for arbitrary current waveforms," IEEE Trans. Ekctron Dedces, vol. 37, pp. 1343-50, 1990.
	8	K. Banerjee, A. Amerasekera, N. Cheung and C. Hu, "High-current failure model for VLSI interconnects under short-pulse stress conditions," IEEE Ekctmn Device Lett., vol. 18, No. 9, pp. 405-407, 1997.
	9	K. Baneriee, A. Amerasekera and C. Hu, "Characterization of VLSI circuit interconnect heating and failure under ESD conditions," Proc. IRPS, 1996, pp. 237-245.
	10	W. R. Hunter, "Self-consistent solutions for allowed interconnect current density - Part I: Implications for technology evolution," IEEE Trans. Ekctron Devices, rot. ED-44, pp. 304-309, 1997.
	11	S. Rzepka, K. Banerjee, E. Meusel, and C. Hu, "Characterization of selfheating in advanced VLSI interconnect lines based on thermal finite element simulation," IEEE Trans. on Components, Packaging and Manufacturing Tecbnology-PartA, vol. 21, No. 3, pp. 1-6, 1998.
	12	J. Ida et al, "Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS," Tecb. Dig. VIA1 Syrup., pp. 59-60, 1994.
	13	K. Banerjee, A. Amerasekera, G. Dixit and C. Hu, "The effect of interconnect scaring and low-k dielectric on the thermal characteristics of the IC metal," in Tech. Dig. IEDM, 1996, pp. 65-68.
	14	Nagaraj NS , Frank Cano , Haldun Haznedar , Duane Young, A practical approach to static signal electromigration analysis, Proceedings of the 35th annual conference on Design automation, p.572-577, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277195]
	15	National Technology Roadmap for Semiconductors (NTRS).
	16	j. R. Black, "Electromigration failure modes in aluminum metallization for semiconductor devices," IEEE Trans. Electron Devices, voI. 57, no. 9, pp. 1587-1594, 1969.
	17	A. A. Bilotti, "Static temperature distribution in IC chips with isothermal heat sources," IEEE Trans. Electron Devices, vol. ED-21, pp. 217-226, 1974.
	18	W. R. Hunter, "Self-consistent solutions for allowed Interconnect current density- Part II: Application to design guidelines," IEEE Trans. Electron Devices, vol. ED-44, pp. 310-316, 1997.
	19	C. Jin, L Ting, K. Taylor, T. Seta, and J. D. Luttmer, "Thermal conductivity measurement of low dielectric constant fdms," in Proc. Second International Dielectrics for I/7_SI/ULSI Multiletel Interconnection Conference (DUMIC), 1996, pp. 21-28.
	20	Private Communications, Professor Kenneth Goodson, Thermosciences Division, Mechanical Eng. Department, Stanford University.
	21	H. A. Schafft, "Thermal analysis of electromigration test structures," IEEE Trans. Electron Devices, vol. ED-34, pp. 664-672, 1987.
	22	Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]
	23	Julian Culetu , Chaim Amir , John MacDonald, A practical repeater insertion method in high speed VLSI circuits, Proceedings of the 35th annual conference on Design automation, p.392-395, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277151]
	24	"Physical design modelling and verification proiect (SPACE Project)", http://cas.et.tudelft.nl/research/space.html
	25	C. Duvvury and A. Amerasekera, "State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs," Semiconductor Sdence. and Tech., pp. 833-850, 1996.
	26	A. Amerasekera and C. Duvvury, "The impact of technology scaling on ESD robustness and protection circuit design," in EOS/ESD Syrup. Proc., 1994, pp. 237-245.
	27	S. H. Voldman, "ESD robustness and scaring impfications of aluminum and copper interconnects in advanced semiconductor technology," in EOS/ESD Symp. Pro~., 1997, pp. 3t6-329.

CITED BY 34

	Kaustav Banerjee , Amit Mehrotra, Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects, Proceedings of the 38th conference on Design automation, p.798-803, June 2001, Las Vegas, Nevada, United States
	Amir H. Ajami , Kaustav Banerjee , Massoud Pedram , Lukas P. P. P. van Ginneken, Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs, Proceedings of the 38th conference on Design automation, p.567-572, June 2001, Las Vegas, Nevada, United States
	Shukri J. Souri , Kaustav Banerjee , Amit Mehrotra , Krishna C. Saraswat, Multiple Si layer ICs: motivation, performance analysis, and design implications, Proceedings of the 37th conference on Design automation, p.213-220, June 05-09, 2000, Los Angeles, California, United States
	Kaustav Banerjee , Massoud Pedram , Amir H. Ajami, Analysis and optimization of thermal issues in high-performance VLSI, Proceedings of the 2001 international symposium on Physical design, p.230-237, April 01-04, 2001, Sonoma, California, United States
	Ting-Yuan Wang , Charlie Chung-Ping Chen, Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method, Proceedings of the 2001 international symposium on Physical design, p.238-243, April 01-04, 2001, Sonoma, California, United States
	X. Xiao , X. You , G. Ruan, Compact quasi-analytic equations for estimating the temperature distribution of ULSI interconnections, Microelectronic Engineering, v.60 n.3-4, p.415-428, April 2002
	Youngsoo Shin , Takayasu Sakurai, Estimation of power distribution in VLSI interconnects, Proceedings of the 2001 international symposium on Low power electronics and design, p.370-375, August 2001, Huntington Beach, California, United States
	R. Streiter , H. Wolf , Z. Zhu , X. Xiao , T. Gessner, Application of combined thermal and electrical simulation for optimization of deep submicron interconnection systems, Microelectronic Engineering, v.60 n.1, p.39-49, January 2002
	Ting Yen Chiang , Kaustav Banerjee , Krishna C. Saraswat, Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Kaustav Banerjee , Amit Mehrotra, Coupled analysis of electromigration reliability and performance in ULSI signal nets, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Amir H. Ajami , Kaustav Banerjee , Massoud Pedram, Analysis of substrate thermal gradient effects on optimal buffer insertion, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Ting-Yuan Wang , Charlie Chung-Ping Chen, Thermal-ADI: a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.691-700, August 2003
	Guoqiang Chen , Sachin Sapatnekar, Partition-driven standard cell thermal placement, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Mario R. Casu , Mariagrazia Graziano , Guido Masera , Gianluca Piccinini , Maurizio Zamboni, An electromigration and thermal model of power wires for a priori high-level reliability prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.349-358, April 2004
	Amir H. Ajami , Kaustav Banerjee , Massoud Pedram, Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.277-290, March 2005
	Ting-Yuan Wang , Yu-Min Lee , Charlie Chung-Ping Chen, 3D thermal-ADI: an efficient chip-level transient thermal simulator, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Peak temperature control and leakage reduction during binding in high level synthesis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Yong Zhan , Brent Goplen , Sachin S. Sapatnekar, Electrothermal analysis and optimization techniques for nanoscale integrated circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Lei Cheng , Liang Deng , Martin D. F. Wong, Floorplanning for 3-D VLSI design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.225-248, June 2002
	A. Chakraborty , P. Sithambaram , K. Duraisami , A. Macii , E. Macii , M. Poncino, Thermal resilient bounded-skew clock tree optimization methodology, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Pilok Lim , Taewhan Kim, Thermal-aware high-level synthesis based on network flow method, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Hao Yu , Yiyu Shi , Lei He , Tanay Karnik, Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Min Ni , Seda Ogrenci Memik, Self-heating-aware optimal wire sizing under Elmore delay model, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Hao Yu , Yu Hu , Chunchen Liu , Lei He, Minimal skew clock embedding considering time variant temperature gradient, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	I-Jye Lin , Tsui-Yee Ling , Yao-Wen Chang, Statistical circuit optimization considering device andinterconnect process variations, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Hao Yu , Joanna Ho , Lei He, Simultaneous power and thermal integrity driven via stapling in 3D ICs, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Peng Li , L. T. Pileggi , M. Asheghi , R. Chandra, Efficient full-chip thermal modeling and analysis, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.319-326, November 07-11, 2004
	Peng Li, Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced Leakage, Proceedings of the 7th International Symposium on Quality Electronic Design, p.254-259, March 27-29, 2006
	Ting-Yuan Wang , Jeng-Liang Tsai , Charlie Chung-Ping Chen, Thermal and Power Integrity Based Power/Ground Networks Optimization, Proceedings of the conference on Design, automation and test in Europe, p.20830, February 16-20, 2004
	Basab Datta , Wayne Burleson, Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Ashutosh Chakraborty , Karthik Duraisami , Ashoka Sathanur , Prassanna Sithambaram , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Dynamic thermal clock skew compensation using tunable delay buffers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.639-649, June 2008
	Basab Datta , Wayne Burleson, Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	N. Spennagallo , L. Codecasa , D. D'Amore , P. Maffezzoni, Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects, Microelectronics Journal, v.40 n.7, p.1154-1159, July, 2009