A floorplan-based planning methodology for power and clock distribution in ASICs

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A floorplan-based planning methodology for power and clock distribution in ASICs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 766 - 771

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Joon-Seo Yim	DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea
Seong-Ok Bae	DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea
Chong-Min Kyung	Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, Korea

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 3

	Su-Wei Wu , Yao-Wen Chang, Efficient power/ground network analysis for power integrity-driven design methodology, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Chen-Wei Liu , Yao-Wen Chang, Floorplan and power/ground network co-synthesis for fast design convergence, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Jens Lienig , Göran Jerke, Current-driven wire planning for electromigration avoidance in analog circuits, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan