Analysis of performance impact caused by power supply noise in deep submicron devices

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Analysis of performance impact caused by power supply noise in deep submicron devices

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 760 - 765

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Yi-Min Jiang	Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA
Kwang-Ting Cheng	Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 30, Citation Count: 20

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R.B. Brashear, N. Menezes, C. Oh, L. T. Pillage, and M. R. Mercer, "Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis," Proceedings of the European Design and Test Conference, pp. 332-337, 1994.
	2	Kwang-Ting Cheng , Angela Krstic , Hsi-Chuan Chen, Generation of High Quality Tests for Robustly Untestable Path Delay Faults, IEEE Transactions on Computers, v.45 n.12, p.1379-1392, December 1996 [doi>10.1109/12.545968]
	3	David E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
	4	Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm," Proc. of IEEE Custom Integrated Circuits Conference, pp. 135-138, May 1997.
	5	H.-F. Jyu, S. Malik, S. Devadas, and K. W. Keutzer, "Statistical Timing Analysis of Combinational Logic Circuits," IEEE Transactions on VLSI Systems, Vol. 1, No 2, pp. 126-137, June 1993.
	6	Horng-Fei Jyu , Sharad Malik, Statistical delay modeling in logic design and synthesis, Proceedings of the 31st annual conference on Design automation, p.126-130, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196304]
	7	SYNOPSYS, "PowerMill Reference Manual," August 1998.
	8	Fred M. Armstrong , Mark R. Reiter , David R. Tryon, Statistical failure analysis of system timing, IBM Journal of Research and Development, v.28 n.4, p.340-355, July 1984
	9	G. de Veciana , M. Jacome , J.-H. Guo, Hierarchical algorithms for assessing probabilistic constraints on system performance, Proceedings of the 35th annual conference on Design automation, p.251-256, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277113]

CITED BY 21

	M. Graziano , M. Delaurenti , M. Zamboni, Power supply design parameters prediction for high performance IC design flows, Proceedings of the 2000 international workshop on System-level interconnect prediction, p.61-67, April 08-09, 2000, San Diego, California, United States
	Sani R. Nassif , Joseph N. Kozhaya, Fast power grid simulation, Proceedings of the 37th conference on Design automation, p.156-161, June 05-09, 2000, Los Angeles, California, United States
	Sani R. Nassif, Modeling and forecasting of manufacturing variations (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation, p.145-150, January 2001, Yokohama, Japan
	Yu Min Lee , Charlie Chung Ping Chen, Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Geng Bai , Sudhakar Bobba , Ibrahim N. Hajj, Static timing analysis including power supply noise effect on propagation delay in VLSI circuits, Proceedings of the 38th conference on Design automation, p.295-300, June 2001, Las Vegas, Nevada, United States
	Tsung-Hao Chen , Charlie Chung-Ping Chen, Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods, Proceedings of the 38th conference on Design automation, p.559-562, June 2001, Las Vegas, Nevada, United States
	Min Zhao , Kaushik Gala , Vladimir Zolotov , Yuhong Fu , Rajendran Panda , R. Ramkumar , Bhuwan Agrawal, Worst case clock skew under power supply variations, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava, High level techniques for power-grid noise immunity, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Davide Bertozzi , Luca Benini , Giovanni De Micheli, Energy-reliability trade-off for NoCs, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Hierarchical power supply noise evaluation for early power grid design prediction, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.183-188, March 31-April 01, 2001, Sonoma, California, United States
	Jing Jia Liou , Angela Krstić , Yi Min Jiang , Kwang Ting Cheng, Path selection and pattern generation for dynamic timing analysis considering power supply noise effects, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.225-248, June 2002
	Kevin T. Tang , Eby G. Friedman, Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.249-259, June 2002
	M. Graziano , G. Piccinini, Statistical power supply dynamic noise prediction in hierarchical power grid and package networks, Integration, the VLSI Journal, v.41 n.4, p.524-538, July, 2008
	Takashi Enami , Shinyu Ninomiya , Masanori Hashimoto, Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Yu Zhong , M. D. F. Wong, Fast algorithms for IR drop analysis in large power grid, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.351-357, November 06-10, 2005, San Jose, CA
	Sanjay Pant , David Blaauw , Vladimir Zolotov , Savithri Sundareswaran , Rajendran Panda, Vectorless Analysis of Supply Noise Induced Delay Variation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.184, November 09-13, 2003
	Yu-Min Lee , Charlie Chung-Ping Chen, The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method, Proceedings of the conference on Design, Automation and Test in Europe, p.11020, March 03-07, 2003
	Jing Wang , Duncan M. (Hank) Walker , Xiang Lu , Ananta Majhi , Bram Kruseman , Guido Gronthoud , Luis Elvira Villagra , Paul J. A. M. van de Wiel , Stefan Eichenberger, Modeling Power Supply Noise in Delay Testing, IEEE Design & Test, v.24 n.3, p.226-234, May 2007
	Weiqing Guo , Yu Zhong , Tom Burd, Context-sensitive static transistor-level IR analysis, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Takashi Enami , Shinyu Ninomiya , Masanori Hashimoto, Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.4, p.541-553, April 2009