Detecting false timing paths

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Detecting false timing paths: experiments on PowerPC microprocessors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 737 - 741

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Richard Raimi	Motorola Corp. 6200 Bridgepoint Pkwy., Austin, TX
Jacob Abraham	Computer Engineering Research Center, The University of Texas at Austin, Austin, TX

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Tapan J. Chakraborty , Vishwani D. Agrawal, Effective Path Selection for Delay Fault Testing of Sequential Circuits, Proceedings of the IEEE International Test Conference, p.998-1003, November 03-05, 1997
	2	A. Biere , A. Cimatti , E. M. Clarke , M. Fujita , Y. Zhu, Symbolic model checking using SAT procedures instead of BDDs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.317-320, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309942]
	3	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
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	5	Hoon Chang , Jacob A. Abraham, An Efficient Critical Path Tracing Algorithm for Designing HighPerformance Vlsi Systems, Journal of Electronic Testing: Theory and Applications, v.11 n.2, p.119-129, Oct. 1997 [doi>10.1023/A:1008214321624]
	6	H. Chang, Strategies for Design and Test of High Pelformance Systems. Ph.D. Dissertation, The University of Texas at Austin, August 1993.
	7	S. Jab, Y. Lu, M. Minea, E. Clarke, Equivalence Checking Using Abstract BDDs, ICCD, 1997.
	8	Yuji Kukimoto , Robert K. Brayton, Exact required time analysis via false path detection, Proceedings of the 34th annual conference on Design automation, p.220-225, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266070]
	9	Carl Seger, VOSS - A Formal Hardware Verification System User''s Guide, University of British Columbia, Vancouver, BC, Canada, 1993
	10	E McGeer, A. Saldanha, R. Brayton, A. Sangiovanni- Vincentelli Delay Models and Exact Timing Analysis. in T. Sasao, editor, Logic Synthesis and Optimization, pp. 167-189, Kluwer Publishers, 1993.

CITED BY 2

	J. Zeng , M. Abadir , J. Bhadra , J. Abraham, Full chip false timing path identification: applications to the PowerPCTM microprocessors, Proceedings of the conference on Design, automation and test in Europe, p.514-519, March 2001, Munich, Germany
	Jing Zeng , Magdy Abadir , Jacob Abraham, False timing path identification using ATPG techniques and delay-based information, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA