Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

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Effects of inductance on the propagation delay and repeater insertion in VLSI circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 721 - 724

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Yehea I. Ismail	Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York
Eby G. Friedman	Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 24, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D.A. Priore, "Inductance on Silicon for Sub-Micron CMOS VLSI," Proceedings of the IEEE Symposium on VLSI Circuits, pp. 17-18, May 1993.
	2	M.P. May, A. Taflove, and J. Baron, "FD-TD Modeling of Digital Signal Propagation in 3-D Circuits with Passive and Active Loads," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-42, No. 8, pp. 1514 - 1523, August 1994.
	3	T. Sakurai, "Approximation of Wiring Delay in MOSFET LSI," IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 4, pp. 418 - 426, August 1983.
	4	G.Y. Yacoub, H. Pham, and E. G. Friedman, "A System for Critical Path Analysis Based on Back Annotation and Distributed Interconnect Impedance Models," Microelectronic Journal, Vol. 18, No. 3, pp. 21 - 30, June 1988.
	5	Masakazu Shoji, High-Speed Digital Circuits, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1996
	6	J. Tortes, "Advanced Copper Interconnections for Silicon CMOS Technologies," Applied Surface Science, Vol. 91, No. 1, pp. 112 - 123, October 1995.
	7	A. Deutsch et al., "When are Transmission-Line Effects Important for On-Chip Interconnections?," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-45, No. 10, pp. 1836-1846, October 1997.
	8	Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Figures of merit to characterize the importance of on-chip inductance, Proceedings of the 35th annual conference on Design automation, p.560-565, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277193]
	9	H.B. Bakoglu and J. D. Meindl, "Optimal Interconnection Circuits for VLSI," IEEE Transactions on Electron Devices, Vol. ED-32, No. 5, pp. 903 - 909, May 1985.
	10	V. Adler and E. G. Friedman, "Repeater Design to Reduce Delay and Power in Resistive Interconnect," IEEE Transactions on Circuits and Systems H: Analog and Digital Signal Processing, Vol. CAS-45, No. 5, pp. 607 - 616, May 1998.
	11	H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, 1990.
	12	L. N. Dworsky, Modern Transmission Line Theory and Applications, John Wiley & Sons, Inc., New York, 1979.
	13	W. C. Elmore, "The Transient Response of Damped Linear Networks," Journal of Applied Physics, Vol. 19, pp. 55 - 63, January 1948.
	14	AS/X User's Guide, IBM Corporation, New York, 1996.

CITED BY 10

	Kaustav Banerjee , Amit Mehrotra, Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects, Proceedings of the 38th conference on Design automation, p.798-803, June 2001, Las Vegas, Nevada, United States
	I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
	Kevin M. Lepak , Irwan Luwandi , Lei He, Simultaneous shield insertion and net ordering under explicit RLC noise constraint, Proceedings of the 38th conference on Design automation, p.199-202, June 2001, Las Vegas, Nevada, United States
	Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Repeater insertion in tree structured inductive interconnect, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.420-424, November 07-11, 1999, San Jose, California, United States
	Atsushi Kurokawa , Nobuto Ono , Tetsuro Kage , Hiroo Masuda, DEPOGIT: dense power-ground interconnect architecture for physical design integrity, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.517-522, January 27-30, 2004, Yokohama, Japan
	Noha Mahmoud , Maged Ghoneima , Yehia Ismail, Physical limitations on the bit-rate of on-chip interconnects, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Akira Tsuchiya , Masanori Hashimoto , Hidetoshi Onodera, Interconnect RL extraction at a single representative frequency, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Zhanyuan Jiang , Shiyan Hu , Jiang Hu , Zhuo Li , Weiping Shi, A new RLC buffer insertion algorithm, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	M. Mondal , Y. Massoud, Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.691-696, November 06-10, 2005, San Jose, CA
	Mosin Mondal , Yehia Massoud, Accurate loop self inductance bound for efficient inductance screening, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.12, p.1393-1397, December 2006