Microprocessor based testing for core-based system on chip

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Microprocessor based testing for core-based system on chip

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 586 - 591

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

C. A. Papachristou	Computer Engineering Program, EECS Dept., Case Western Reserve University, Cleveland, OH
F. Martin	Computer Engineering Program, EECS Dept., Case Western Reserve University, Cleveland, OH
M. Nourani	Computer Engineering Program, EECS Dept., Case Western Reserve University, Cleveland, OH

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 12, Citation Count: 10

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F.P.M. Beenker, R.G. Bennetts and A.P. Thijssen, "Testability Concepts for Digital ICs, The Macro Teat Approach," Kluwer Acad. Publishers, 1995.
	2	Lee Whetsel, An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores, Proceedings of the IEEE International Test Conference, p.69-78, November 03-05, 1997
	3	K. De, 1.1 Test methodology for embedded cores which protects intellectual property, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.2, April 27-May 01, 1997
	4	R. Chandramouli , Stephen Pateras, Testing systems on a chip, IEEE Spectrum, v.33 n.11, p.42-47, Nov. 1996 [doi>10.1109/6.542274]
	5	Indradeep Ghosh , Niraj K. Jha , Sujit Dey, A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems, Proceedings of the IEEE International Test Conference, p.50-59, November 03-05, 1997
	6	V. Immaneni and S. Raman, "Direct Access Teat Scheme - Design of Block and Core Cells for Embedded ASICs," Intern. Test Conf. (ITC-90), pp. 488- 492, Oct. 1990.
	7	M. Nourani , C. Papachristou, 1.3 Parallelism in Structural Fault Testing of Embedded Cores, Proceedings of the 16th IEEE VLSI Test Symposium, p.15, April 26-30, 1998
	8	Nur A. Touba , Bahram Pouya, Testing Embedded Cores Using Partial Isolation Rings, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.10, April 27-May 01, 1997
	9	Bahram Pouya , Nur A. Touba, Modifying User-Defined Logic for Test Access to Embedded Cores, Proceedings of the IEEE International Test Conference, p.60-68, November 03-05, 1997
	10	"VSI Alliance", Architecture Document, Version 1.0, 1997.
	11	A. J. van de Goor , Th. J. W. Verhallen, Functional Testing of Current Microprocessors (applied to the Intel i860TM), Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.684-695, September 20-24, 1992
	12	Joep Aerts , Erik Jan Marinissen, Scan chain design for test time reduction in core-based ICs, Proceedings of the 1998 IEEE International Test Conference, p.448-457, October 18-22, 1998

CITED BY 10

	Sungbae Hwang , Jacob A. Abraham, Selective-run built-in self-test using an embedded processor, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Mehrdad Nourani , Amir Attarha, Built-in self-test for signal integrity, Proceedings of the 38th conference on Design automation, p.792-797, June 2001, Las Vegas, Nevada, United States
	F. Corno , M. Sonza Reorda , S. Squillero , M. Violante, On the test of microprocessor IP cores, Proceedings of the conference on Design, automation and test in Europe, p.209-213, March 2001, Munich, Germany
	Seongmoon Wang , Srimat T. Chakradhar , Balakrishnan Kedarnath, Re-configurable embedded core test protocol, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.234-237, January 27-30, 2004, Yokohama, Japan
	Leticia Bolzani , Ernesto Sanchez , Massimiliano Schillaci , Giovanni Squillero, Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores, Proceedings of the 9th annual conference on Genetic and evolutionary computation, July 07-11, 2007, London, England
	P. Bernardi , M. Rebaudengo , M. Sonza Reorda , M. Violante, A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories, Proceedings of the conference on Design, Automation and Test in Europe, p.10720, March 03-07, 2003
	F. Corno , G. Cumani , M. Sonza Reorda , G. Squillero, Fully Automatic Test Program Generation for Microprocessor Cores, Proceedings of the conference on Design, Automation and Test in Europe, p.11006, March 03-07, 2003
	P. Bernardi , G. Masera , F. Quaglio , M. Sonza Reorda, Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study, Proceedings of the conference on Design, Automation and Test in Europe, p.228-233, March 07-11, 2005
	Leticia M. V. Bolzani , Edgar E. Sanchez , Matteo Sonza Reorda, A software-based methodology for the generation of peripheral test sets based on high-level descriptions, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
	Fawnizu Azmadi Hussin , Tomokazu Yoneda , Alex OrailoĞLu , Hideo Fujiwara, Scheduling Power-Constrained Tests through the SoC Functional Bus, IEICE - Transactions on Information and Systems, v.E91-D n.3, p.736-746, March 2008