A methodology for the verification of a “system on chip”

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A methodology for the verification of a “system on chip”

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 574 - 579

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Daniel Geist	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Giora Biran	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Tamara Arons	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Michael Slavkin	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Yvgeny Nustov	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Monica Farkas	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Karen Holtz	IBM Haifa Research Lab, MATAM Advanced Technology Center, Haifa, Israel
Andy Long	IBM Field Design Center, Essex Junction, VT
Dave King	IBM Field Design Center, Essex Junction, VT
Steve Barret	IBM Field Design Center, Essex Junction, VT

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 22, Citation Count: 3

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Aharon Aharon , Dave Goodman , Moshe Levinger , Yossi Lichtenstein , Yossi Malka , Charlotte Metzger , Moshe Molcho , Gil Shurek, Test program generation for functional verification of PowerPC processors in IBM, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.279-285, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217542]
	2	A. Aharon , B. Dorfman , E. Gofman , M. Leibowitz , V. Schwartzburd , A. Bar-David, Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generator, IBM Systems Journal, v.30 n.4, p.527-538, 1991
	3	G. Biran. MAL Functional Spec.. HDG, Haifa, ISRAEL, 1997.
	4	A. Chandra , V. Iyengar , D. Jameson , R. Jawalekar , I. Nair , B. Rosen , M. Mullen , J. Yoon , R. Armoni , D. Geist , Y. Wolfsthal, AVPGEN—a test generator for architecture verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.188-200, June 1995 [doi>10.1109/92.386220]
	5	Raanan Grinwald , Eran Harel , Michael Orgad , Shmuel Ur , Avi Ziv, User defined coverage—a tool supported methodology for design verification, Proceedings of the 35th annual conference on Design automation, p.158-163, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277081]
	6	C. May, E. Silha, R. Simpson, and H. Warren, editors. The PowerPC Architecture. Morgan Kaufmann, 1994.
	7	A.Mesh, EmaclI Functional Spec., HDG, Haifa, ISRAEL, 1997.
	8	M. Schaffer and E. Green. On-Chip Peripheral Bus Specification. PowerPC Embedded Proceesor Solutions, RTR NC, Mar. 1996.
	9	M. Schaffer and J. Revilla. PowerPC 4XX Local Bus Specification. PowerPC Embedded Proceesor Solutions, RTR NC, Oct. 1996.

CITED BY 3

	Marinés Puig-Medina , Gülbin Ezer , Pavlos Konas, Verification of configurable processor cores, Proceedings of the 37th conference on Design automation, p.426-431, June 05-09, 2000, Los Angeles, California, United States
	Jun Yuan , Ken Albin , Adnan Aziz , Carl Pixley, Simplifying Boolean constraint solving for random simulation-vector generation, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.123-127, November 10-14, 2002, San Jose, California
	Bruno Monsuez , Franck Védrine , Micaela Mayero , Nicolas Vallé, How an "incoherent behavior" inside generic hardware component characterizes functional errors, Proceedings of the 8th WSEAS international conference on Artificial intelligence, knowledge engineering and data bases, p.477-483, February 21-23, 2009, Cambridge, UK