Low-power behavioral synthesis optimization using multiple precision arithmetic

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Low-power behavioral synthesis optimization using multiple precision arithmetic

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 568 - 573

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Milos Ercegovac	Computer Science Department, University of California, Los Angeles
Darko Kirovski	Computer Science Department, University of California, Los Angeles
Miodrag Potkonjak	Computer Science Department, University of California, Los Angeles

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 33, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Ber97	http://www-cad.eecs.berkeley.edu/Software/
	Bli97	J.F. Blinn. Fugue for MMX. IEEE Computer Graphics and Applications, vol.17, (no.2), pp.88-93, 1997.
	Cha92	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	Che96	W. Chen, et. al. Native signal processing on the Ultrasparc in the Ptolemy environment. Asilomar Conference on Signals, Systems and Computers, vol.2, pp.1368-72, 1997.
	Erc96	M. Ercegovac, D. Kirovski, G. Mustafa, M. Potkonjak. Low- Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. Technical Report, Computer Science Department, University of California, Los Angeles, 1996.
	Gar79	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	Gol96	G. Goldman , P. Tirumalai, UltraSPARC-II: the advancement of ultracomputing, Proceedings of the 41st IEEE International Computer Conference, p.417, February 25-28, 1996
	Jah97	B. Jahne. SIMD image processing algorithms with the Intel multimedia extension instruction set. Automatisierungstechnik, vol.45, (no.10), pp.453-60, 1997.
	Kar93	W. Karmer. Multiple-precision computations with result verification. Scientific computing with automatic result verification, Academic Press, pp.325-56, 1993.
	Lak98	Ganesh Lakshminarayana , Niraj K. Jha, Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions, Proceedings of the 35th annual conference on Design automation, p.439-444, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277167]
	Lee97	C. Lee , D. Kirovski , I. Hong , M. Potkonjak, DSP Quant: Design, Validation, and Applications of DSP Hard Real-Time Benchmark, Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1, p.679, April 21-24, 1997
	Lou95	Marianne E. Louie , Miloš D. Ercegovac, A variable-precision square root implementation for field programmable gate arrays, The Journal of Supercomputing, v.9 n.3, p.315-336, 1995 [doi>10.1007/BF01212874]
	Mou96	Z.J.A. Mou, D.S. Rice, D. Wei. VIS-based native video processing on UltraSPARC. International Conference on Image Processing, pp.153-6, 1996.
	Pel96	Alex Peleg , Uri Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, v.16 n.4, p.42-50, August 1996 [doi>10.1109/40.526924]
	Pot92	Miodrag Potkonjak , Jan Rabaey, Maximally fast and arbitrarily fast implementation of linear computations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.304-308, November 1992, Santa Clara, California, United States
	Pot95	M. Potkonjak, M.B. Srivastava. Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations. International Conference on Application Specific Array Processors, p.45-56, 1994.
	Rag94	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	Sal89	A. Salz , M. Horowitz, IRSIM: an incremental MOS switch-level simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.173-178, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74412]
	Sch95	Michael J. Schulte , Earl E. Swartzlander, Jr., Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor, Proceedings of the 12th Symposium on Computer Arithmetic, p.222, July 19-21, 1995
	Sin95	D. Singh, et al. Power conscious CAD tools and methodologies: a perspective. Proc. of the IEEE, vol.83, (no.4), pp.570-94, 1995.
	Smi96	David M. Smith, A multiple-precision division algorithm, Mathematics of Computation, v.65 n.213, p.157-163, Jan. 1996 [doi>10.1090/S0025-5718-96-00688-6]
	Tak95	N. Takagi. A multiple-precision modular multiplication algorithm with triangle additions. IEICE Transactions on Information and Systems, vol.E78, 1995.
	Zho95	Chang-Guo Zhou , Ihtisham Kabir , Leslie Kohn , Aman Jabbi , D. Rice , Xio-Ping Hu, MPEG video decoding with the UltraSPARC visual instruction set, Proceedings of the 40th IEEE Computer Society International Conference, p.470, March 05-09, 1995

CITED BY 13

	G. Constantinides , P. Cheung , W. Luk, Heuristic datapath allocation for multiple wordlength systems, Proceedings of the conference on Design, automation and test in Europe, p.791-797, March 2001, Munich, Germany
	M. C. Molina , J. M. Mendías , R. Hermida, Bit-level scheduling of heterogeneous behavioural specifications, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.602-608, November 10-14, 2002, San Jose, California
	M. C. Molina , J. M. Mendías , R. Hermida, High-level synthesis of multiple-precision circuits independent of data-objects length, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Qin Zhao , Bart Mesman , Twan Basten, Static resource models for code-size efficient embedded processors, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.219-250, May 2003
	M. C. Molina , J. M. Mendías , R. Hermida, Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.12-15, p.505-519, December 2003
	Regina Berretta , Carlos Cotta , Pablo Moscato, Enhancing the performance of memetic algorithms by using a matching-based recombination algorithm, Metaheuristics: computer decision-making, Kluwer Academic Publishers, Norwell, MA, 2004
	Deming Chen , Jason Cong , Yiping Fan, Low-power high-level synthesis for FPGA architectures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	N. Julien , S. Gailhard , E. Martin, Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT, Journal of VLSI Signal Processing Systems, v.35 n.2, p.195-211, September 2003
	G. A. Constantinides , P. Y. K. Cheung , W. Luk, Synthesis of saturation arithmetic architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.3, p.334-354, July 2003
	M. C. Molina , J. M. Mendias , R. Hermida, High-Level Allocation to Minimize Internal Hardware Wastage, Proceedings of the conference on Design, Automation and Test in Europe, p.10264, March 03-07, 2003
	Vijay Raghunathan , Mani B. Srivastava , Milos D. Ercegovac , Anand Raghunathan, High-Level Synthesis with SIMD Units, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.407, January 07-11, 2002
	M. C. Molina , R. Ruiz-Sautua , J. M. Mendías , R. Hermida, Behavioural Bitwise Scheduling Based on Computational Effort Balancing, Proceedings of the conference on Design, automation and test in Europe, p.10684, February 16-20, 2004
	M. C. Molina , R. Ruiz-Sautua , P. García-Repetto , J. M. Mendías, Performance-driven scheduling of behavioural specifications, Integration, the VLSI Journal, v.42 n.3, p.294-303, June, 2009