| Interconnect estimation and planning for deep submicron designs |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
table of contents
New Orleans, Louisiana, United States
Pages: 507 - 510
Year of Publication: 1999
ISBN:1-58133-109-7
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Authors
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Jason Cong
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Department of Computer Science, University of California, Los Angeles, CA
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David Zhigang Pan
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Department of Computer Science, University of California, Los Angeles, CA
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| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 16, Citation Count: 14
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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
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J. Gong and D. Z. Pan, "Interconnect delay estimation models for synthesis and design planning," in Proc. Asia and South Pacific Design Automation Conf., pp. 97-100, Jan., 1999.
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J. Cong and D. Z. Pan, "Interconnect estimation and planning for deep submicron designs," Tech. Rep. 980035, UCLA CS Dept, 1998. http://cadlab.cs.ucla.edu/~,,pan/publications/.
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Jason Cong , Lei He , Cheng-Kok Koh , Zhigang Pan, Global interconnect sizing and spacing with consideration of coupling capacitance, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.628-633, November 09-13, 1997, San Jose, California, United States
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Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1997.
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J. Davis and ,}. Meindl, "Is interconnect the weak link?," IEEE Circuits and Devices Magazine, vol. 14, no. 2, pp. 30-36, 1998.
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P. Fisher and R. Nesbitt, "The test of time. clock-cycle estimation and test challenges for future microprocessors," IEEE Circuits and Devices Magazine, vol. 14, pp. 37-44, March 1998.
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Jason Cong , Lei He , Andrew B. Kahng , David Noice , Nagesh Shirali , Steve H.-C. Yen, Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology, Proceedings of the 34th annual conference on Design automation, p.627-632, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266303]
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W. C. Elmore, "The transient response of damped linear networks with particular regard to wide-band amplifiers," Journal of Applied Physics, vol. 19, pp. 55-63, Jan. 1948.
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J. Davis, V. De, and J. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI) i. derivation and validation," IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 580-9, 1998.
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CITED BY 14
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Jason Cong , Sung Kyu Lim , Chang Wu, Performance driven multi-level and multiway partitioning with retiming, Proceedings of the 37th conference on Design automation, p.274-279, June 05-09, 2000, Los Angeles, California, United States
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Ankireddy Nalamalpu , Wayne Burleson, Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters, Proceedings of the 2001 international symposium on Physical design, p.204-211, April 01-04, 2001, Sonoma, California, United States
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Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester, Improved a priori terconnect predictions and technology extrapolation in the GTX system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.3-14, February 2003
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Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Sudhakar Muddu , Dirk Stroobandt , Dennis Sylvester, Effects of global interconnect optimizations on performance estimation of deep submicron design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Ashok Jagannathan , Hannah Honghua Yang , Kris Konigsfeld , Dan Milliron , Mosur Mohan , Michail Romesis , Glenn Reinman , Jason Cong, Microarchitecture evaluation with floorplanning and interconnect pipelining, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Jason Cong , Ashok Jagannathan , Glenn Reinman , Yuval Tamir, Understanding the energy efficiency of SMT and CMP with multiclustering, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
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Jason Cong , Ashok Jagannathan , Yuchun Ma , Glenn Reinman , Jie Wei , Yan Zhang, An automated design flow for 3D microarchitecture evaluation, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
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Jason Cong , Ashok Jagannathan , Glenn Reinman , Michail Romesis, Microarchitecture evaluation with physical planning, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Yen-Wei Wu , Chia-Lin Yang , Ping-Hung Yuh , Yao-Wen Chang, Joint exploration of architectural and physical design spaces with thermal consideration, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
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M-C. Frank Chang , Jason Cong , Adam Kaplan , Chunyue Liu , Mishali Naik , Jagannath Premkumar , Glenn Reinman , Eran Socher , Sai-Wang Tam, Power reduction of CMP communication networks via RF-interconnects, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.376-387, November 08-12, 2008
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