Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

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Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 502 - 506

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Chung-Ping Chen	Strategic CAD Labs, Design Technology, Intel Corporation, Hillsboro, OR
Noel Menezes	Strategic CAD Labs, Design Technology, Intel Corporation, Hillsboro, OR

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 20, Citation Count: 17

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 17

	Y. Gao , D. Wong, A graph based algorithm for optimal buffer insertion under accurate delay models, Proceedings of the conference on Design, automation and test in Europe, p.535-539, March 2001, Munich, Germany
	I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
	Minghorng Lai , D. F. Wong, Memory-efficient interconnect optimization, Proceedings of the 2001 conference on Asia South Pacific design automation, p.198-202, January 2001, Yokohama, Japan
	Jason Cong , David Zhigang Pan , Prasanna V. Srinivas, Improved crosstalk modeling for noise constrained interconnect optimization, Proceedings of the 2001 conference on Asia South Pacific design automation, p.373-378, January 2001, Yokohama, Japan
	Yu-Min Lee , Charlie Chung-Ping Chen, Hierarchical model order reduction for signal-integrity interconnect synthesis, Proceedings of the 11th Great Lakes symposium on VLSI, p.109-114, March 2001, West Lafayette, Indiana, United States
	P. Sarkar , C. Koh, Repeater block planning under simultaneous delay and transition time constraints, Proceedings of the conference on Design, automation and test in Europe, p.540-545, March 2001, Munich, Germany
	Pasquale Cocchini, Concurrent flip-flop and repeater insertion for high performance integrated circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.268-273, November 10-14, 2002, San Jose, California
	Weiping Shi , Zhuo Li , Charles J. Alpert, Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.609-614, January 27-30, 2004, Yokohama, Japan
	Magdy A. El-Moursy , Eby G. Friedman, Optimum wire sizing of RLC interconnect with repeaters, Integration, the VLSI Journal, v.38 n.2, p.205-225, December 2004
	Masanori Hashimoto , Masao Takahashi , Hidetoshi Onodera, Crosstalk noise optimization by post-layout transistor sizing, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Yuantao Peng , Xun Liu, Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Yuantao Peng , Xun Liu, A sensitivity analysis of low-power repeater insertion, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Murat Becer , Ravi Vaidyanathan , Chanhee Oh , Rajendran Panda, Signal integrity management in an SoC physical design flow, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Zhuo Li , C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi, Making fast buffer insertion even faster via approximation techniques, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yuantao Peng , Xun Liu, Low-power repeater insertion with both delay and slew rate constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Salim Chowdhury , John Lillis, Repeater insertion for concurrent setup and hold time violations with power-delay trade-off, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Haoxing Ren , D. Z. Pan , P. G. Villarubia, True crosstalk aware incremental placement with noise map, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.402-409, November 07-11, 2004