A novel VLSI layout fabric for deep sub-micron applications

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A novel VLSI layout fabric for deep sub-micron applications

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 491 - 496

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Sunil P. Khatri
Amit Mehrotra
Robert K. Brayton
Ralf H. J. M. Otten
Alberto Sangiovanni-Vincentelli

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 18, Citation Count: 33

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Andrew B. Kahng, Design technology productivity in the DSM era (invited talk), Proceedings of the 2001 conference on Asia South Pacific design automation, p.443-448, January 2001, Yokohama, Japan
	Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Ralph H. J. M. Otten , Giuseppe S. Garcea, Are wires plannable?, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.59-66, March 31-April 01, 2001, Sonoma, California, United States
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Routing methodology for minimizing 1nterconnect energy dissipation, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Robert K. Brayton, The future of logic synthesis and verification, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Reduction of coupling effects by optimizing the 3-D configuration of the routing grid, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.951-954, October 2003
	Wilsin Gosti , Sunil P. Khatri , Alberto L. Sangiovanni-Vincentelli, Addressing the timing closure problem by integrating logic optimization and placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Sudhakar Muddu , Dirk Stroobandt , Dennis Sylvester, Effects of global interconnect optimizations on performance estimation of deep submicron design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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	R. Streiter , H. Wolf , Z. Zhu , X. Xiao , T. Gessner, Application of combined thermal and electrical simulation for optimization of deep submicron interconnection systems, Microelectronic Engineering, v.60 n.1, p.39-49, January 2002
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