Reducing cross-coupling among interconnect wires in deep-submicron datapath design

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Reducing cross-coupling among interconnect wires in deep-submicron datapath design

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 485 - 490

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Joon-Seo Yim	DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea
Chong-Min Kyung	Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, Korea

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 25, Citation Count: 21

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 21

	Ki-Wook Kim , Unni Narayanan , Sung-Mo Kang, Domino logic synthesis minimizing crosstalk, Proceedings of the 37th conference on Design automation, p.280-285, June 05-09, 2000, Los Angeles, California, United States
	Q. Yu , E. Kuh, Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements, Proceedings of the conference on Design, automation and test in Europe, p.445-450, March 2001, Munich, Germany
	D. Deschacht , G. Servel, On-chip interconnections: impact of adjacent lines on timing, Proceedings of the 2001 conference on Asia South Pacific design automation, p.539-544, January 2001, Yokohama, Japan
	Lei He , Kevin M. Lepak, Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization, Proceedings of the 2000 international symposium on Physical design, p.55-60, May 2000, San Diego, California, United States
	Kei Hirose , Hiroto Yasuura, A bus delay reduction technique considering crosstalk, Proceedings of the conference on Design, automation and test in Europe, p.441-445, March 27-30, 2000, Paris, France
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Routing methodology for minimizing 1nterconnect energy dissipation, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Reduction of coupling effects by optimizing the 3-D configuration of the routing grid, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.951-954, October 2003
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware interconnect power optimization in domino logic synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.79-89, February 2003
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware power optimization for on-chip interconnect, Proceedings of the 2000 international symposium on Low power electronics and design, p.108-113, July 25-27, 2000, Rapallo, Italy
	P. Bazargan-Sabet , F. Ilponse, Modeling crosstalk noise for deep submicron verification tools, Proceedings of the conference on Design, automation and test in Europe, p.530-534, March 2001, Munich, Germany
	Srinivasa R. Sridhara , Naresh R. Shanbhag, Coding for system-on-chip networks: a unified framework, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Kevin M. Lepak , Min Xu , Jun Chen , Lei He, Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.3, p.290-309, July 2004
	Bret Victor , Kurt Keutzer, Bus encoding to prevent crosstalk delay, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Yi-Ci Cai , Xin Zhao , Qiang Zhou , Xian-Long Hong, Shielding area optimization under the solution of interconnect crosstalk, Journal of Computer Science and Technology, v.20 n.6, p.901-906, November 2005
	K. Najeeb , Vishal Gupta , V. Kamakoti, Delay and peak power minimization for on-chip buses using temporal redundancy, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Nallamothu Satyanarayana , Madhu Mutyam , A Vinaya Babu, Exploiting on-chip data behavior for delay minimization, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Serkan Ozdemir , Arindam Mallik , Ja Chun Ku , Gokhan Memik , Yehea Ismail, Variable latency caches for nanoscale processor, Proceedings of the 2007 ACM/IEEE conference on Supercomputing, November 10-16, 2007, Reno, Nevada
	Chunjie Duan , Sunil P. Khatri, Exploiting Crosstalk to Speed up On-Chip Buses, Proceedings of the conference on Design, automation and test in Europe, p.20778, February 16-20, 2004
	Roberto Gómez , Alejandro Girón , Victor H. Champac, A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines, Journal of Electronic Testing: Theory and Applications, v.24 n.6, p.529-538, December 2008
	Madhu Mutyam, Selective shielding: a crosstalk-free bus encoding technique, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Madhu Mutyam, Selective shielding technique to eliminate crosstalk transitions, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.3, p.1-20, May 2009