Buffer insertion with accurate gate and interconnect delay computation

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Buffer insertion with accurate gate and interconnect delay computation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 479 - 484

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Charles J. Alpert	IBM Austin Research Laboratory, Austin, TX
Anirudh Devgan	IBM Austin Research Laboratory, Austin, TX
Stephen T. Quay	IBM Server Group, Austin, TX

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 29, Citation Count: 34

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Charles Alpert , Anirudh Devgan, Wire segmenting for improved buffer insertion, Proceedings of the 34th annual conference on Design automation, p.588-593, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266291]
	2	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion for noise and delay optimization, Proceedings of the 35th annual conference on Design automation, p.362-367, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277145]
	3	Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267712]
	4	Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
	5	Jason Cong , Cheng-Kok Koh, Interconnect layout optimization under higher-order RLC model, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.713-720, November 09-13, 1997, San Jose, California, United States
	6	S. Dhar and M. A. Franklin, "Optimum Buffer Circuits for Driving Long Uniform Lines", IEEE Journal of Solid-State Circuits, 26(1), 1991, pp. 32-40.
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	14	L. T. Pillage and R. A. Rohrer. Asymptotic Waveform Evaluation for Timing Analysis. IEEE TCAD, 9(4), 1990, 352-366.
	15	J. Qian, S. Pulllela, and L. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates", IEEE Trans. CAD,. 13(12), 1994, pp. 1526-1535.
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CITED BY 34

	Minghorng Lai , D. F. Wong, Memory-efficient interconnect optimization, Proceedings of the 2001 conference on Asia South Pacific design automation, p.198-202, January 2001, Yokohama, Japan
	Tong Xiao , Malgorzata Marek-Sadowska, Functional correlation analysis in crosstalk induced critical paths identification, Proceedings of the 38th conference on Design automation, p.653-656, June 2001, Las Vegas, Nevada, United States
	Charles Alpert , Chris Chu , Gopal Gandham , Miloš Hrkić , Jiang Hu , Chandramouli Kashyap , Stephen Quay, Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Is wire tapering worthwhile?, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.430-436, November 07-11, 1999, San Jose, California, United States
	Y. Gao , D. Wong, A graph based algorithm for optimal buffer insertion under accurate delay models, Proceedings of the conference on Design, automation and test in Europe, p.535-539, March 2001, Munich, Germany
	Sani R. Nassif, Modeling and forecasting of manufacturing variations (embedded tutorial), Proceedings of the 2001 conference on Asia South Pacific design automation, p.145-150, January 2001, Yokohama, Japan
	Youxin Gao , D. F. Wong, A fast and accurate delay estimation method for buffered interconnects, Proceedings of the 2001 conference on Asia South Pacific design automation, p.533-538, January 2001, Yokohama, Japan
	Rajeev Murgai, Technology-based transformations, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Sani R. Nassif, Designing closer to the edge (tutorial), Proceedings of the conference on Design, automation and test in Europe, p.636-639, March 27-30, 2000, Paris, France
	Magdy A. El-Moursy , Eby G. Friedman, Shielding effect of on-chip interconnect inductance, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Pasquale Cocchini, Concurrent flip-flop and repeater insertion for high performance integrated circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.268-273, November 10-14, 2002, San Jose, California
	Xiaodong Yang , Chung Kuan Cheng , Walter H. Ku , Robert J. Carragher, Hurwitz stable reduced order modeling for RLC interconnect trees, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Weiping Shi , Zhuo Li , Charles J. Alpert, Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.609-614, January 27-30, 2004, Yokohama, Japan
	Renato F. Hentschke , Jagannathan Narasimhan , David Kung, Improving run times by pruned application of synthesis transforms, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	Jiang Hu , Charles J. Alpert , Stephen T. Quay , Gopal Gandham, Buffer insertion with adaptive blockage avoidance, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Yuantao Peng , Xun Liu, Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi, Path based buffer insertion, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Zhuo Li , C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi, Making fast buffer insertion even faster via approximation techniques, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Charles J. Alpert , Miloš Hrkić , Stephen T. Quay, A fast algorithm for identifying good buffer insertion candidate locations, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Xiao-Dong Yang , Chung-Kuan Cheng , Walter H. Ku , Robert Carragher, Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.193-208, June 2002
	Yifang Liu , Jiang Hu , Weiping Shi, Multi-scenario buffer insertion in multi-core processor designs, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	C. J. Alpert , Miloš Hrkić , J. Hu , A. B. Kahng , J. Lillis , B. Liu , S. T. Quay , S. S. Sapatnekar , A. J. Sullivan , P. Villarrubia, Buffered Steiner trees for difficult instances, Proceedings of the 2001 international symposium on Physical design, p.4-9, April 01-04, 2001, Sonoma, California, United States
	Yuantao Peng , Xun Liu, Low-power repeater insertion with both delay and slew rate constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Shiyan Hu , Charles J. Alpert , Jiang Hu , Shrirang Karandikar , Zhuo Li , Weiping Shi , C. N. Sze, Fast algorithms for slew constrained minimum cost buffering, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Salim Chowdhury , John Lillis, Repeater insertion for concurrent setup and hold time violations with power-delay trade-off, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Zhanyuan Jiang , Shiyan Hu , Jiang Hu , Zhuo Li , Weiping Shi, A new RLC buffer insertion algorithm, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Bruce Tseng , Hung-Ming Chen, Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Supratik Chakraborty , Rajeev Murgai, Layout-driven Timing Optimization by Generalized De Morgan Transform, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.647, January 07-11, 2002
	Xun Liu , Yuantao Peng , Marios C. Papaefthymiou, RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power, Proceedings of the conference on Design, Automation and Test in Europe, p.1330-1335, March 07-11, 2005
	Nikolai Ryzhenko , Oleg Venger, A practical repeater insertion flow, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Zhuo Li , Charles J. Alpert , Shiyan Hu , Tuhin Muhmud , Stephen T. Quay , Paul G. Villarrubia, Fast interconnect synthesis with layer assignment, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Jae-sun Seo , Igor L. Markov , Dennis Sylvester , David Blaauw, On the decreasing significance of large standard cells in technology mapping, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Yibo Wang , Yici Cai , Xianlong Hong , Yi Zou, Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.5, p.1028-1037, May 2007