Wave steering in YADDs

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Wave steering in YADDs: a novel non-iterative synthesis and layout technique

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 466 - 471

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Arindam Mukherjee	Dept. of ECE, University of California, Santa Barbara, CA
Ranganathan Sudhakar	Dept. of ECE, Stanford University, Stanford, CA
Malgorzata Marek-Sadowska	Dept. of ECE, University of California, Santa Barbara, CA
Stephen I. Long	Dept. of ECE, University of California, Santa Barbara, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 12

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	W.EBurleson, M.Ciesielski,F.Klass and W.Liu, "Wave-Pipelining a Tutorial and Research Survey"; IEEE Transactions on VLSI Systems, Vol.6, No.3, Sep. 1998.
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	9	W.K.C.Lam, R.K.Brayton and A.L.Sangiovanni-Vincentelli, "Valid Clock Frequencies and Their Computation in Wavepipelined Circuits", IEEE Transactions on CAD of IC and Systems, Vol. 15, No.7, July 1996.
	10	ES.Lassen, S.I.Long, and K.R.Nary, "Ultra-Low Power GaAs MESFET MSI Circuits Using Two-Phase Dynamic FET Logic", IEEE J. Solid State Circuits, Vol.28, pp.1038-1045, October 1993.
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	12	M. Perkowski, L.Jozwiak and R.Drechsler, "Two hierarchies of generalized Kronecker trees, forms, decision diagrams and regular layouts", Proc. 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, (Reed- Muller'97), Sept. 19-20, 1997, Oxford, UK.
	13	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	14	M. Shamanna et al, "Multiple-input, Multiple-output Pass Transistor Logic", Int'l J. Electronics, vol. 79, no. 1, pp. 33-45.
	15	R.Sudhakar, "YADDA: Layout Synthesis using Pass Transistor Logic", MS Thesis, UCSB, 1998.
	16	K.Yano et al, "A 3.8ns CMOS 16x16b Multiplier using Complementary Pass-Transistor Logic", IEEE J.Solid-State Circuits, vol.25, no.2, pp.388-395, April, 1990.
	17	Information Sciences Institute, MOS Implementation Service www.mosis.com Bloomington IN, 1995.

CITED BY 12

	Luca Macchiarulo , Shih-Ming Shu , Malgorzata Marek-Sadowska, Wave steered FSMs, Proceedings of the conference on Design, automation and test in Europe, p.270-276, March 27-30, 2000, Paris, France
	Amit Singh , Arindam Mukherjee , Luca Macchiarulo , Malgorzata Marek-Sadowska, PITIA: an FPGA for throughput-intensive applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.354-363, June 2003
	Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Interconnect pipelining in a throughput-intensive FPGA architecture, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.153-160, February 2001, Monterey, California, United States
	Amit Singh , Luca Macchiarulo , Arindam Mukherjee , Malgorzata Marek-Sadowska, A novel high throughput reconfigurable FPGA architecture, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.22-29, February 10-11, 2000, Monterey, California, United States
	Luca Macchiarulo , Malgorzata Marek-Sadowska, Wave-steering one-hot encoded FSMs, Proceedings of the 37th conference on Design automation, p.357-360, June 05-09, 2000, Los Angeles, California, United States
	Arindam Mukherjee , Malgorzata Marek-Sadowska, Wave steering to integrate logic and physical syntheses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.105-120, February 2003
	Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Latency and latch count minimization in wave steered circuits, Proceedings of the 38th conference on Design automation, p.383-388, June 2001, Las Vegas, Nevada, United States
	Rolf Drechsler , Junhao Shi , Görschwin Fey, MuTaTe: an efficient design for testability technique for multiplexor based circuits, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Rüdiger Ebendt , Wolfgang Günther , Rolf Drechsler, Minimization of the expected path length in BDDs based on local changes, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.865-870, January 27-30, 2004, Yokohama, Japan
	Montek Singh , Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: high-capacity style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.11, p.1270-1283, November 2007
	Rudiger Ebendt , Wolfgang Gunther , Rolf Drechsler, Combination of Lower Bounds in Exact BDD Minimization, Proceedings of the conference on Design, Automation and Test in Europe, p.10758, March 03-07, 2003
	Rüdiger Ebendt , Rolf Drechsler, Weighted A∗ search -- unifying view and application, Artificial Intelligence, v.173 n.14, p.1310-1342, September, 2009