Gradient-based optimization of custom circuits using a static-timing formulation

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Gradient-based optimization of custom circuits using a static-timing formulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 452 - 459

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

A. R. Conn	IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY
I. M. Elfadel	IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY
W. W. Molzen, Jr.	IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY
P. R. O'Brien	IBM Electronic Design Automation, 11400 Burnet Road, M. S. 9460, Austin, TX
P. N. Strenski	IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY
C. Visweswariah	IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY
C. B. Whan	IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 23, Citation Count: 18

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	W. Nye, D. C. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits, "DE- LIGHT.SPICE: An optimization-based system for the design of integrated circuits," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-7, pp. 501-519, April 1988.
	2	Andrew R. Conn , Ruud A. Haring , Chandu Visweswariah , Chai Wah Wu, Circuit optimization via adjoint Lagrangians, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.281-288, November 09-13, 1997, San Jose, California, United States
	3	A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu, "JiffyTune: circuit optimization using time-domain sensitivities," IEEE Transactions on Computer-Aided Design of lCs and Systems, vol. 17, pp. 1292- 1309, December 1998.
	4	J. P. Fishburn and A. E. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," IEEE International Conference on Computer-Aided Design, pp. 326-328, November 1985.
	5	W. C. Elmore, "The transient analysis of damped linear networks with particular regard to wideband amplifiers," Journal of Applied Physics, vol. 19, no. 1, pp. 55- 63, 1948.
	6	R Penfield and J. Rubinstein, "Signal delay in RC tree networks," in Proceedings of the 2nd Caltech VLSI Conference, pp. 269-283, March 1981.
	7	S. S. Sapatnekar, V. B. Rao, R M. Vaidya, and S. M. Kang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Transactions on Computer-Aided Design of lCs and Systems, vol. CAD-12, pp. 1621-1634, November 1993.
	8	A. Srinivasan, K. Chaudhary, and E. S. Kuh, "RITUAL: A performance driven placement algorithm for small cell ICs," IEEE International Conference on Computer-Aided Design, pp. 48-51, November 1991.
	9	A. R. Conn , N. I. M. Gould , Ph L. Toint, Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A), Springer-Verlag New York, Inc., Secaucus, NJ, 1992
	10	C. Visweswariah and R. A. Rohrer, "Piecewise approximate circuit simulation," IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 10, pp. 861-870, July 1991.
	11	Chandramouli Visweswariah , Jalal A. Wehbeh, Incremental event-driven simulation of digital FET circuits, Proceedings of the 30th international conference on Design automation, p.737-741, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165111]
	12	R Feldmann, T. V. Nguyen, S. W. Director, and R. A. Rohrer, "Sensitivity computation in piecewise approximate circuit simulation," IEEE Transactions on Computer-Aided Design of lCs and Systems, vol. 10, pp. 171-183, February 1991.
	13	A. R. Conn , I. M. Gould , Ph. L. Toint, Global convergence of a class of trust region algorithms for optimization with simple bounds, SIAM Journal on Numerical Analysis, v.25 n.2, p.433-460, April 1988 [doi>10.1137/0725029]
	14	Andrew R. Conn , Nicholas I. M. Gould , Philippe L. Toint, A globally convergent augmented Lagrangian algorithm for optimization with general constraints and simple bounds, SIAM Journal on Numerical Analysis, v.28 n.2, p.545-572, April 1991 [doi>10.1137/0728030]
	15	Andrew R. Conn , Luís N. Vicente , Chandu Visweswariah, Two-Step Algorithms for Nonlinear Optimization with Structured Applications, SIAM Journal on Optimization, v.9 n.4, p.924-947, 1999 [doi>10.1137/S1052623498334396]
	16	Miles Ohlrich , Carl Ebeling , Eka Ginting , Lisa Sather, SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm, Proceedings of the 30th international conference on Design automation, p.31-37, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164556]
	17	João P. Marques Silva , Karem A. Sakallah, GRASP—a new search algorithm for satisfiability, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.220-227, November 10-14, 1996, San Jose, California, United States
	18	C. C. Douglas, D. A. George, and M. E. Henderson, "Object classes for numerical analysis," in P1vceedings of the second annual object-oriented numerics conference, pp. 32-49, Rogue Wave Software, Inc., Corvallis Oregon, April 1994.
	19	Andrew R. Conn , Ruud A. Haring , Chandu Visweswariah, Noise considerations in circuit optimization, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.220-227, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288617]

CITED BY 18

	Gregory A. Northrop , Pong-Fei Lu, A semi-custom design flow in high-performance microprocessor design, Proceedings of the 38th conference on Design automation, p.426-431, June 2001, Las Vegas, Nevada, United States
	Mahadevamurty Nemani , Vivek Tiwari, Macro-driven circuit design methodology for high-performance datapaths, Proceedings of the 37th conference on Design automation, p.661-666, June 05-09, 2000, Los Angeles, California, United States
	Yiu-Hing Chan , Prabhakar Kudva , Lisa Lacey , Greg Northrop , Thomas Rosser, Physical synthesis methodology for high performance microprocessors, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Hiroaki Yoshida , Kaushik De , Vamsi Boppana, Accurate pre-layout estimation of standard cell characteristics, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	V. Zyuban , P. N. Strenski, Balancing hardware intensity in microprocessor pipelines, IBM Journal of Research and Development, v.47 n.5-6, p.585-598, September 2003
	Victor Zyuban , Sameh W. Asaad , Thomas W. Fox , Anne-Marie Haen , Daniel Littrell , Jaime H. Moreno, Design methodology for semi custom processor cores, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Andrew R. Conn , Chandu Visweswariah, Overview of continuous optimization advances and applications to circuit tuning, Proceedings of the 2001 international symposium on Physical design, p.74-81, April 01-04, 2001, Sonoma, California, United States
	Chandu Visweswariah , Andrew R. Conn, Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.244-252, November 07-11, 1999, San Jose, California, United States
	Victor Zyuban , Philip Strenski, Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	J. H. Moreno , V. Zyuban , U. Shvadron , F. D. Neeser , J. H. Derby , M. S. Ware , K. Kailas , A. Zaks , A. Geva , S. Ben-David , S. W. Asaad , T. W. Fox , D. Littrell , M. Biberstein , D. Naishlos , H. Hunter, An innovative low-power high-performance programmable signal processor for digital communications, IBM Journal of Research and Development, v.47 n.2-3, p.299-326, March 2003
	Hiran Tennakoon , Carl Sechen, Efficient and accurate gate sizing with piecewise convex delay models, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Robert W. Brodersen , Mark A. Horowitz , Dejan Markovic , Borivoje Nikolic , Vladimir Stojanovic, Methods for true power minimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.35-42, November 10-14, 2002, San Jose, California
	Andreas Wächter , Chandu Visweswariah , Andrew R. Conn, Large-scale nonlinear optimization in circuit tuning, Future Generation Computer Systems, v.21 n.8, p.1251-1262, October 2005
	Xiaoliang Bai , Chandu Visweswariah , Philip N. Strenski, Uncertainty-aware circuit optimization, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Ian Kuon , Jonathan Rose, Area and delay trade-offs in the circuit and architecture design of FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	G. Mayer , G. Doettling , R. F. Rizzolo , C. J. Berry , S. M. Carey , C. M. Carney , J. Keinert , P. Loeffler , W. Nop , D. E. Skooglund , V. A. Victoria , A. P. Wagstaff , P. M. Williams, Design methods for attaining IBM System z9 processor cycle-time goals, IBM Journal of Research and Development, v.51 n.1/2, p.19-35, January 2007
	Jurjen Westra , Dirk-Jan Jongeneel , Ralph H. J. M. Otten , Chandu Visweswariah, Time Budgeting in a Wireplanning Context, Proceedings of the conference on Design, Automation and Test in Europe, p.10436, March 03-07, 2003
	Ian Kuon , Jonathan Rose, Automated transistor sizing for FPGA architecture exploration, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California