Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

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Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 436 - 441

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Supamas Sirichotiyakul	Advanced Tools, Motorola Inc., Austin, TX
Tim Edwards	Advanced Tools, Motorola Inc., Austin, TX
Chanhee Oh	Advanced Tools, Motorola Inc., Austin, TX
Jingyan Zuo	Advanced Tools, Motorola Inc., Austin, TX
Abhijit Dharchoudhury	Advanced Tools, Motorola Inc., Austin, TX
Rajendran Panda	Advanced Tools, Motorola Inc., Austin, TX
David Blaauw	Advanced Tools, Motorola Inc., Austin, TX

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 40, Citation Count: 39

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 39

	Dennis Sylvester , Himanshu Kaul, Future performance challenges in nanometer design, Proceedings of the 38th conference on Design automation, p.3-8, June 2001, Las Vegas, Nevada, United States
	Luca Benini , Giovanni De Micheli, Logic synthesis for low power, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Mongkol Ekpanyapong , Sung Kyu Lim, Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	David Nguyen , Abhijit Davare , Michael Orshansky , David Chinnery , Brandon Thompson , Kurt Keutzer, Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Ruchir Puri , Leon Stok , John Cohn , David Kung , David Pan , Dennis Sylvester , Ashish Srivastava , Sarvesh Kulkarni, Pushing ASIC performance in a power envelope, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Mahesh Ketkar , Sachin S. Sapatnekar, Standby power optimization via transistor sizing and dual threshold voltage assignment, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.375-378, November 10-14, 2002, San Jose, California
	Rajeev Rao , Ashish Srivastava , David Blaauw , Dennis Sylvester, Statistical estimation of leakage current considering inter- and intra-die process variation, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Akihito Sakanaka , Seiichirou Fujii , Toshinori Sato, A leakage-energy-reduction technique for highly-associative caches in embedded systems, ACM SIGARCH Computer Architecture News, v.32 n.3, p.50-54, June 2004
	W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Ashish Srivastava , Dennis Sylvester , David Blaauw, Statistical optimization of leakage power considering process variations using dual-Vth and sizing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Rajeev Rao , Ashish Srivastava , David Blaauw , Dennis Sylvester, Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.131-139, February 2004
	Ashish Srivastava , Dennis Sylvester , David Blaauw, Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Michael Liu , Wei-Shen Wang , Michael Orshansky, Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Sarvesh H. Kulkarni , Dennis Sylvester, High performance level conversion for dual VDD design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.926-936, September 2004
	James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California
	Dongwoo Lee , David Blaauw , Dennis Sylvester, Gate oxide leakage current analysis and reduction for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.155-166, February 2004
	Hongliang Chang , Sachin S. Sapatnekar, Full-chip analysis of leakage power under process variations, including spatial correlations, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Yuh-Fang Tsai , David E. Duarte , N. Vijaykrishnan , Mary Jane Irwin, Characterization and modeling of run-time techniques for leakage power reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.11, p.1221-1232, November 2004
	D. G. Chinnery , K. Keutzer, Closing the power gap between ASIC and custom: an ASIC perspective, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Sarvesh Bhardwaj , Sarma B. K. Vrudhula, Leakage minimization of nano-scale circuits in the presence of systematic and random variations, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Sarvesh Bhardwaj , Yu Cao , Sarma Vrudhula, Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Murari Mani , Anirudh Devgan , Michael Orshansky, An efficient algorithm for statistical minimization of total power under timing yield constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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	Chang-woo Kang , Massoud Pedram, Technology mapping for low leakage power and high speed with hot-carrier effect consideration, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	De-Shiuan Chiou , Shih-Hsin Chen , Shih-Chieh Chang , Chingwei Yeh, Timing driven power gating, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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