Vertical benchmarks for CAD

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Vertical benchmarks for CAD

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 36th annual ACM/IEEE Design Automation Conference table of contents

New Orleans, Louisiana, United States

Pages: 408 - 413

Year of Publication: 1999

ISBN:1-58133-109-7

Authors

Christopher Inacio	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Herman Schmit	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
David Nagle	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Andrew Ryan	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Donald E. Thomas	Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Yingfai Tong	Motorola, Austin, TX and Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Ben Klass	Cognex, Cambridge, MA and Dept. of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 17, Citation Count: 0

Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Brglez, D. Bryan, K. Kozminski. "Combinational Profiles of Sequential Benchmark Circuits", ISCAS '89, pp. 1929-1934, 1989.
	2	Joel Darnauer , Wayne Wei-Ming Dai, A method for generating random circuits and its application to routability measurement, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.66-72, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228380]
	3	N. Dutt. "Current Status of HLSW Benchmarks and Guidelines for Benchmark Submission", HLSynth '92 Benchmark, Sept. 1992.
	4	Michael Hutton , J. P. Grossman , Jonathan Rose , Derek Corneil, Characterization and parameterized random generation of digital circuits, Proceedings of the 33rd annual conference on Design automation, p.94-99, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240537]
	5	Motorola Corporation, DSP56000 Digital Signal Processor Family Manual. 1995.
	6	Programmable Electronics Performance Corporation, URL: http://www.prep.org/synth.htm.
	7	System Performance Evaluation Corporation (SPEC), SPEC CPU95 Version 1.1, URL: http://www.spec.org, August 21, 1995.
	8	S. Yang. "Logic Synthesis and Optimization Benchmarks User Guide, Version 3.0", Microelectronics Center of North Carolina, Research Triangle Park, NC, Jan. 1991.